OPA191_0017 Datasheet, PDF (21/51 Pages) Texas Instruments – 36-V, Low Power, Precision, CMOS, Rail-to-Rail Input/Output, Low Offset Voltage, Low Input Bias Current Op Amp

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OPA191, OPA2191, OPA4191
SBOS701A – DECEMEBER 2015 – REVISED APRIL 2016
Input Offset Voltage Drift (continued)
Instead of the box method, a convenient way to illustrate input offset drift is to compute the slopes of the input
offset voltage versus temperature curve. This is the same as computing the input offset drift at each point along
the input offset voltage versus temperature curve. The results for the OPAx191 family are illustrated in Figure 50.
1.2
0.9
0.6
+3 1
0.3
1
0
-1
-0.3
-0.6
-0.9
-1.2
±75 ±50 ±25
-3 1
0 25 50 75 100 125 150
Temperature (ƒC)
C001
Figure 50. Input Offset Voltage Drift vs Temperature
(SOIC Package)
As illustrated in Figure 50, the input offset drift is typically less than ±0.3 µV/°C over the range from –40°C to
+125°C. When performing an error analysis over the full specified temperature range, use the typical and
maximum values for input offset voltage drift as described in the Electrical Characteristics tables. If a reduced
temperature range is applicable, use the information illustrated in Figure 50 when performing an error analysis.
To determine the change in input offset voltage, use Equation 1:
ΔV_OS = ΔT × dV_OS/dT
where
• ΔV_OS = Change in input offset voltage
• ΔT = Change in temperature
• dV_OS/dT = Input offset voltage drift
(1)
For example, determine the amount of OPA191ID input offset voltage change over the temperature range of
25°C to 75°C for 1 σ (68%) of the units. As shown in Figure 50, the input offset drift is typically 0.25 µV/°C. This
input offset drift results in a typical input offset voltage change of (75°C – 25°C) × 0.25 µV/°C = 12.5 µV.
For 3 σ (99.7%) of the units, Figure 50 shows a typical input offset drift of approximately 0.75 µV/°C. This input
offset drift results in a typical input offset voltage change of (75°C – 25°C) × 0.75 µV/°C = 37.5 µV.
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