MSP430FE42XA_14 Datasheet, PDF (21/50 Pages) Texas Instruments – MIXED SIGNAL MICROCONTROLLER

MSP430FE42xA
MIXED SIGNAL MICROCONTROLLER
SLAS588 -- FEBRUARY 2008
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
wake-up LPM3
PARAMETER
t_d(LPM3) Delay time
TEST CONDITIONS
V_CC
f = 1 MHz
f = 2 MHz
3V
f = 3 MHz
MIN TYP MAX UNIT
6
6 μs
6
RAM (see Note 1)
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
VRAMh
CPU halted (see Note 1)
1.6
V
NOTE 1: This parameter defines the minimum supply voltage when the data in the program memory RAM remain unchanged. No program
execution should take place during this supply voltage condition.
LCD
PARAMETER
V₍₃₃₎
V₍₂₃₎
V₍₁₃₎
V_{(33) --} V₍₀₃₎
I_(R03)
I_(R13)
I_(R23)
V_(Sxx0)
V_(Sxx1)
V_(Sxx2)
V_(Sxx3)
Analog voltage
Input leakage
Segment line
voltage
TEST CONDITIONS
Voltage at R33
Voltage at R23
Voltage at R13
V_CC = 3 V
Voltage at R33/R03
R03 = V_SS
R13 = V_CC/3
R23 = 2 × V_CC/3
No load at all
segment and
common lines,
V_CC = 3 V
I_(Sxx) = --3 μA,
V_CC = 3 V
MIN
2.5
2.5
V₍₀₃₎
V₍₁₃₎
V(₂₃₎
V(₃₃₎
TYP
MAX
V_CC +0.2
(V₃₃--V₀₃) × 2/3 + V₀₃
(V₍₃₃₎--V₍₀₃₎) × 1/3 + V₍₀₃₎
V_CC +0.2
±20
±20
±20
V₍₀₃₎ -- 0.1
V₍₁₃₎ -- 0.1
V₍₂₃₎ -- 0.1
V₍₃₃₎ + 0.1
UNIT
V
nA
V
USART0 (see Note 1)
PARAMETER
TEST CONDITIONS
MIN NOM MAX UNIT
t_(τ)
USART0: deglitch time
V_CC = 3 V, SYNC = 0, UART mode
150 280 500 ns
NOTE 1:
The signal applied to the USART0 receive signal/terminal (URXD0) should meet the timing requirements of t_(τ) to ensure that the URXS
flip-flop is set. The URXS flip-flop is set with negative pulses meeting the minimum-timing condition of t_(τ). The operating conditions to
set the flag must be met independently from this timing constraint. The deglitch circuitry is active only on negative transitions on the
URXD0 line.
POR brownout, reset (see Notes 1 and 2)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
t_d(BOR)
V_CC(start)
dV_CC/dt ≤ 3 V/s (see Figure 6)
2000 μs
0.7 × V_{(B_IT--)}
V
V_{(B_IT--)}
V_{hys(B_IT--)}
Brownout
dV_CC/dt ≤ 3 V/s (see Figure 6, Figure 7, Figure 8)
dV_CC/dt ≤ 3 V/s (see Figure 6)
1.71
V
70
130
180 mV
t_(reset)
NOTES:
Pulse length needed at RST/NMI pin to accepted reset internally,
V_CC = 3 V
2
μs
1. The current consumption of the brownout module is already included in the I_CC current consumption data. The voltage level V_{(B_IT--)}
+ V_{hys(B_IT--)} is ≤ 1.8 V.
2. During power up, the CPU begins code execution following a period of t_d(BOR) after V_CC = V_{(B_IT--)} + V_{hys(B_IT--)}.
The default FLL+ settings must not be changed until V_CC ≥ V_CC(min), where V_CC(min) is the minimum supply voltage for the desired
operating frequency. See the MSP430x4xx Family User’s Guide (SLAU056) for more information on the brownout/SVS circuit.
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