LMR14050 Datasheet, PDF (21/31 Pages) Texas Instruments – LMR14050 SIMPLE SWITCHER 40 V 5 A, 2.2 MHz Step-Down Converter with 40 μA IQ

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LMR14050
SNVSAA6A – FEBRUARY 2015 – REVISED MARCH 2015
10 Power Supply Recommendations
The LMR14050 is designed to operate from an input voltage supply range between 4 V and 40 V. This input
supply should be able to withstand the maximum input current and maintain a stable voltage. The resistance of
the input supply rail should be low enough that an input current transient does not cause a high enough drop at
the LMR14050 supply voltage that can cause a false UVLO fault triggering and system reset. If the input supply
is located more than a few inches from the LMR14050, additional bulk capacitance may be required in addition to
the ceramic input capacitors. The amount of bulk capacitance is not critical, but a 47 μF or 100 μF electrolytic
capacitor is a typical choice .
11 Layout
11.1 Layout Guidelines
Layout is a critical portion of good power supply design. The following guidelines will help users design a PCB
with the best power conversion performance, thermal performance, and minimized generation of unwanted EMI.
1. The feedback network, resistor R_FBT and R_FBB, should be kept close to the FB pin. V_OUT sense path away
from noisy nodes and preferably through a layer on the other side of a shielding layer .
2. The input bypass capacitor C_IN must be placed as close as possible to the VIN pin and ground. Grounding
for both the input and output capacitors should consist of localized top side planes that connect to the GND
pin and PAD .
3. The inductor L should be placed close to the SW pin to reduce magnetic and electrostatic noise.
4. The output capacitor, C_OUT should be placed close to the junction of L and the diode D. The L, D, and C_OUT
trace should be as short as possible to reduce conducted and radiated noise and increase overall efficiency.
5. The ground connection for the diode, C_IN, and C_OUT should be as small as possible and tied to the system
ground plane in only one spot (preferably at the C_OUT ground point) to minimize conducted noise in the
system ground plane
6. For more detail on switching power supply layout considerations see Application Note AN-1149
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