LDC1000-Q1_16 Datasheet, PDF (21/40 Pages) Texas Instruments – Inductance to Digital Converter

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LDC1000-Q1
SLOS886B – SEPTEMBER 2014 – REVISED OCTOBER 2014
7.6.1.6 Clock Configuration (offset = 0x05) [reset = 0x01]
Figure 22. Clock Configuration Register
7
6
5
4
3
Reserved
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
2
1
0
CLK_SEL
CLK_PD
R/W
R/W
Table 7. Clock Configuration Field Descriptions
Bit Field
7-2 Resrved
1
CLK_SEL
0
CLK_PD
Type
—
R/W
Reset
—
0x01
R/W
0x01
Description
Reserved to 0
1:External crystal used for frequency counter (XIN or
XOUT).
0:External time-base clock used for frequency counter
(TBCLK).
1:Disable external time base clock. Crystal oscillator
power down.
0:Enable External time base clock.
7.6.1.7 Comparator Threshold High LSB (offset = 0x06) [reset = 0xFF]
Figure 23. Comparator Threshold High LSB Register
7
6
5
4
Threshold
High[7:0]
Threshold
High[6]
Threshold
High[5]
Threshold
High[4]
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
3
Threshold
High[3]
R/W
2
Threshold
High[2]
R/W
1
Threshold
High[1]
R/W
0
Threshold
High[0]
R/W
Table 8. Comparator Threshold High LSB Field Descriptions
Bit Field
7:0 Threshold High LSB
Threshold High[7:0]
Type
R/W
Reset
0xFF
Description
Least Significant byte (LSB) of the threshold high register. This
register is a buffer. A read reflects the current value of the
threshold high[7:0] register. See the Comparator Threshold High
MSB (offset = 0x07) [reset = 0xFF] section for details on
updating the threshold high register.
7.6.1.8 Comparator Threshold High MSB (offset = 0x07) [reset = 0xFF]
Figure 24. Comparator Threshold High MSB Register
7
6
5
4
Threshold
High[15]
Threshold
High[14]
Threshold
High[13]
Threshold
High[12]
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
3
Threshold
High[11]
R/W
2
Threshold
High[10]
R/W
1
Threshold
High[9]
R/W
0
Threshold
High[8]
R/W
Table 9. Comparator Threshold High MSB Field Descriptions
Bit Field
7:0 Threshold High MSB
Threshold High[15:8]
Type
R/W
Reset
0xFF
Description
Most significant byte (MSB) of the threshold high register. A
write to this register copies the contents of the 0x06 register and
writes to the threshold high register[15:0]. A read returns the
threshold high [15:8] register. To update the threshold high
register write register 0x06 first and then 0x07.
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