DSD1792A_08 Datasheet, PDF (21/57 Pages) Texas Instruments – 24-BIT, 192-KHZ SAMPLING, ADVANCED SEGMENT, AUDIO STEREO DIGITAL-TO-ANALOG CONVERTER

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DSD1792A
SLES106B − FEBRUARY 2004 − REVISED NOVEMBER 2006
yesMODE CONTROL REGISTERS
User-Programmable Mode Controls
The DSD1792A includes a number of user-programmable functions which are accessed via mode control registers. The
registers are programmed using the serial control interface, which was previously discussed in this data sheet. Table 2 lists
the available mode-control functions, along with their default reset conditions and associated register index.
Table 2. User-Programmable Function Controls
FUNCTION
DEFAULT
REGISTER
BIT
Digital attenuation control
0 dB to –120 dB and mute, 0.5 dB/step
0 dB
Register 16 ATL[7:0] (for L-ch)
Register 17 ATR[7:0] (for R-ch)
Attenuation load control—Disabled, enabled
Input audio data format selection
16-, 20-, 24-bit standard (right-justified) format
24-bit MSB-first left-justified format
16-/24-bit I2S format
Attenuation disabled
24-bit I2S format
Register 18 ATLD
Register 18 FMT[2:0]
Sampling rate selection for de-emphasis
Disabled, 44.1 kHz, 48 kHz, 32 kHz
De-emphasis disabled Register 18 DMF[1:0]
De-emphasis control—Disabled, enabled
De-emphasis disabled Register 18 DME
Soft mute control—Mute disabled, enabled
Mute disabled
Register 18 MUTE
Output phase reversal—Normal, reverse
Normal
Register 19 REV
Attenuation speed selection
×1 fS, ×(1/2) fS, ×(1/4) fS, ×(1/8) fS
DAC operation control—Enabled, disabled
×1 fS
Register 19 ATS[1:0]
DAC operation enabled Register 19 OPE
Zero flag pin operation control
DSD data input, zero flag output
DSD data input
Register 19 ZOE
Stereo DF bypass mode select
Monaural, stereo
Monaural
Register 19 DFMS
Digital filter rolloff selection
Sharp rolloff, slow rolloff
Sharp rolloff
Register 19 FLT
Infinite zero mute control
Disabled, enabled
Disabled
Register 19 INZD
System reset control
Reset operation, normal operation
Normal operation
Register 20 SRST
DSD interface mode control
DSD enabled, disabled
Disabled
Register 20 DSD
Digital-filter bypass control
DF enabled, DF bypass
DF enabled
Register 20 DFTH
Monaural mode selection
Stereo, monaural
Stereo
Register 20 MONO
Channel selection for monaural mode data
L-channel, R-channel
L-channel
Register 20 CHSL
Delta-sigma oversampling rate selection
×64 fS, ×128 fS, ×32 fS
PCM zero output enable
×64 fS
Enabled
Register 20 OS[1:0]
Register 21 PCMZ
DSD zero output enable
Disabled
Register 21 DZ[1:0]
Function available only for read
Zero detection flag
Not zero, zero detected
Not zero = 0
Zero detected = 1
Register 22 ZFGL (for L-ch)
ZFGR (for R-ch)
Device ID (at TDMCA)
—
Register 23 ID[4:0]
(1) _{When in DSD mode, DMF[1:0] is defined as DSD filter (analog FIR) performance selection.}
(2) _{When in DSD mode, OS[1:0] is defined as DSD filter (analog FIR) operation rate selection.}
PCM
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
DSD
DF
BYPASS
yes
yes(1)
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes(2) yes
yes
yes
yes
yes
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