DP83867CS Datasheet, PDF (21/114 Pages) Texas Instruments – High Immunity, Small Form Factor 10/100/1000 Ethernet Physical Layer Transceiver

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DP83867CS, DP83867IS, DP83867E
SNLS504 – OCTOBER 2015
9.4 Device Functional Modes
9.4.1 MAC Interfaces
The DP83867 supports connection to an Ethernet MAC via the following interfaces: SGMII and RGMII.
The SGMII Enable (LED_0) strap allows the user to turn on/off the SGMII MAC interface. The SGMII Enable
strap corresponds to the SGMII Enable (bit 11) in the PHYCR register (address 0x0010).
The SGMII enable has higher priority than the RGMII enable. Table 3 is the configuration table for the MAC
interfaces:
Table 3. Configuration Table for the MAC Interfaces
SGMII ENABLE (Register 0x0010, bit 11)
0x1
0x1
0x0
RGMII ENABLE (Register 0x0032, bit 7)
0x1
0x0
0x1
DEVICE FUNCTIONAL MODE
SGMII
SGMII
RGMII
The initial strap values for the SGMII enable and the RGMII disable are also available in the Strap Configuration
Status Register 1 (STRAP_STS1).
9.4.1.1 Serial GMII (SGMII)
The Serial Gigabit Media Independent Interface (SGMII) provides a means of conveying network data and port
speed between a 100/1000 PHY and a MAC with significantly less signal pins (4 or 6 pins) than required for GMII
(24 pins) or RGMII (12 pins). The SGMII interface uses 1.25Gbps LVDS differential signaling which has the
added benefit of reducing EMI emissions relative to GMII or RGMII.
Since the internal clock/data recovery circuitry (CDR) of DP83867 can detect the transmit timing of the SGMII
data, TX_CLK is not required. SGMII interface is capable of working as a 4-wire or 6-wire SGMII interface. The
default SGMII connection is via four wires. Two differential pairs are used for the transmit and receive
connections. Clock and data recovery are performed in the MAC and in the PHY so no additional differential pair
is required for clocking. Alternately, if the MAC is not capable of recovering the clock from the SGMII receive
data, the DP83867 can be configured to provide the SGMII receive clock via a differential pair
The 1.25Gbps rate of SGMII is excessive for 100Mbps operation. When operating in 100 Mbps mode, the PHY
"elongates" the frame by replicating each frame byte 10 times. This frame elongation takes place "above" the
IEEE 802.3 PCS layer, thus the start of frame delimiter only appears once per frame.
The SGMII interface includes Auto-Negotiation capability. Auto-Negotiation provides a mechanism for control
information to be exchanged between the PHY and the MAC. This allows the interface to be automatically
configured based on the media speed mode resolution on the MDI side. In MAC loopback mode, the SGMII
speed is determined by the MDI speed selection. The SGMII interface works in both Auto-Negotiation and forced
speed mode during the MAC loopback operation. SGMII Auto-Negotiation is the default mode of the operation.
The SGMII Auto-Negotiation process can be disabled and the SGMII speed mode can be forced to the MDI
resolved speed. The SGMII forced speed mode can be enabled with the MDI auto-negotiation or MDI manual
speed mode. SGMII Auto-Negotiation can be disabled via the SGMII_AUTONEG_EN register bit in the CFG2
register (address 0x0014).
The 10M_SGMII_RATE_ADAPT bit (bit 7) of 10M_SGMII_CFG register (0x016F) needs to be cleared for
enabling 10M SGMII operation.
SGMII is enabled via a resistor strap option. See Strap Configuration for details.
All SGMII connections should be AC coupled via an 0.1µF capacitor.
The connection diagrams for 4-wire SGMII and 6-wire SGMII are shown in Figure 11 and Figure 12.
Copyright © 2015, Texas Instruments Incorporated
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