DLPC3430 Datasheet, PDF (21/59 Pages) Texas Instruments – Display Controller

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VSYNC_WE
HSYNC_CS
DATAEN_CMD
HSYNC_CS
DATAEN_CMD
PDATA(23/15:0)
PCLK
t_{p_vsw}
t_{p_vbp}
1 Frame
DLPC3430, DLPC3435
DLPS038B – JULY 2014 – REVISED FEBRUARY 2016
(This diagram assumes the VSYNC
active edge is the rising edge)
t_{p_vfp}
t_{p_hsw}
t_{p_hbp}
1 Line
(This diagram assumes the HSYNC
active edge is the rising edge)
t_{p_hfp}
P0
P1
P2
P3
P
n-2
P
n-1
Pn
Figure 4. Parallel Interface Frame Timing
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