ADS8866_14 Datasheet, PDF (21/42 Pages) Texas Instruments – 16-Bit, 100-kSPS, Serial Interface, microPower, Miniature Single-Ended Input, SAR Analog-to-Digital Converter

ADS8866
www.ti.com
SBAS614A – MAY 2013 – REVISED DECEMBER 2013
When conversion is complete, the device enters acquisition phase and powers down. DIN (functioning as CS)
can be brought low after the maximum conversion time (t_conv-max) elapses. On the DIN falling edge, DOUT comes
out of 3-state and the device outputs the MSB of the data. The lower data bits are output on subsequent SCLK
falling edges. Data are valid on both SCLK edges. Data are valid on both edges of SCLK and can be captured
on either edge. However, a digital host capturing data on the SCLK falling edge can achieve a faster reading rate
(provided t_{h_CK_DO} is acceptable). DOUT goes to 3-state after the 16th SCLK falling edge or when DIN goes high,
whichever occurs first.
As shown in Figure 47, multiple devices can be hooked together on the same data bus. In this case, as shown in
Figure 48, the DIN of the second device (functioning as CS for the second device) can go low after the first
device data are read and the DOUT of the first device is in 3-state.
Care must be taken so that CONVST and DIN are not both low together at any time during the cycle.
CONVST
DIN
DOUT
SCLK
CONVST
DIN
DOUT
SCLK
CS1
CS2
CNV
SDI
ADC #1
ADC #2
CLK
Digital Host
Figure 47. Connection Diagram: Two ADCs with 4-Wire CS Mode
CONVST
DIN
(ADC 1)
DIN
(ADC 2)
SCLK
t_conv-min
t_conv-max
DIN = 1
DIN = 1
1/f_sample
t_ACQ
œœ
1
2 15
16
œœ
17
18 31
32
DOUT
ADC Acquiring
STATE ^{Sample N}
Converting
Sample N
End-of-
Conversion
œœ
D15
D14 D1
D0
œœ
Read Sample N
ADC 1
œœ
D15
D14 D1
D0
œœ
Read Sample N
ADC 2
Acquiring Sample N+1
Figure 48. Interface Timing Diagram: Two ADCs with 4-Wire CS Mode
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: ADS8866
Submit Documentation Feedback
21