ADS5541 Datasheet, PDF (21/37 Pages) Texas Instruments – 14-Bit, 105MSPS Analog-To-Digital Converter

Production Data
ADS5541
www.ti.com
SBAS307C – MAY 2004 – REVISED FEBRUARY 2007
APPLICATION INFORMATION
THEORY OF OPERATION
The ADS5541 is a low-power, 14-bit, 105MSPS,
CMOS, switched capacitor, pipeline ADC that
operates from a single 3.3V supply. The conversion
process is initiated by a falling edge of the external
input clock. Once the signal is captured by the input
S&H, the input sample is sequentially converted by a
series of small resolution stages, with the outputs
combined in a digital correction logic block. Both the
rising and the falling clock edges are used to
propagate the sample through the pipeline every half
clock cycle. This process results in a data latency of
17.5 clock cycles, after which the output data is
available as a 14-bit parallel word, coded in either
straight offset binary or binary two’s complement
format.
INPUT CONFIGURATION
The analog input for the ADS5541 consists of a
differential
sample-and-hold
architecture
implemented using the switched capacitor technique
shown in Figure 39.
S_3a
INP
INM
L₁
R_1a
CP₁
S_1a
C_A
L₂
R_1b
S_1b
CP₂
C_1a
S₂
C_1b
CP₃
R₃
CP₄
L₁, L₂: 6 nH − 10 nH effective
S_3b
R_1a, R_1b: 5W − 8W
C_1a, C_1b: 2.2 pF − 2.6 pF
CP₁, CP₂: 2.5 pF − 3.5 pF
CP₃, CP₄: 1.2 pF − 1.8 pF
C_A: 0.8 pF − 1.2 pF
R₃: 80 W − 120 W
Swithches: S_1a, S_1b: On Resistance: 35 W − 50 W
S₂: On Resistance: 7.5 W − 15 W
S_3a, S_3b: On Resistance: 40 W − 60 W
All switches OFF Resistance: 10 GW
NOTE: All Switches are ON in sampling phase, which is approximately one-half of a clock period.
Figure 39. Analog Input Stage
VINCM
1V
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