ADC128S102QML-SP_17 Datasheet, PDF (21/32 Pages) Texas Instruments – Radiation Hardened 8-Channel, 50 kSPS to 1 MSPS, 12-Bit A/D Converter

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8 Application and Implementation
ADC128S102QML-SP
SNAS411O – AUGUST 2008 – REVISED AUGUST 2016
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The ADC128S102 device is a low-power, eight-channel 12-bit ADC with ensured performance specifications from
50 kSPS to 1 MSPS. It is appropriate to utilize the ADC128S102 at sample rates below 50 kSPS by powering the
device down (de-asserting CSB) in between conversions. The Electrical Characteristics information highlights the
clock frequency where the ADC’s performance is ensured. There is no limitation on periods of time for shutdown
between conversions.
8.2 Typical Application
A typical application is shown in Figure 38. The split analog and digital supply pins are both powered in this
example by the Texas Instruments LP2950-N low-dropout voltage regulator. The analog supply is bypassed with
a capacitor network located close to the ADC128S102. The digital supply is separated from the analog supply by
an isolation resistor and bypassed with additional capacitors. The ADC128S102 uses the analog supply (V_A) as
its reference voltage, so it is very important that V_A be kept as clean as possible. Due to the low power
requirements of the ADC128S102, it is also possible to use a precision reference as a power supply.
51:
LP2950
5V
0.1 PF
1.0 PF
0.1 PF
1.0 PF
0.1 PF
1 PF
INPUT
22:
1 nF
V_D
V_A
IN0
SCLK
.
CS
.
.
ADC128S102
DIN
IN7
DOUT
AGND
DGND
MICROPROCESSOR
DSP
Figure 38. Typical Application Circuit
8.2.1 Design Requirements
A positive supply only data acquisition system capable of digitizing up to eight single-ended input signals ranging
from 0 to 5 V with BW = 10 kHz and a throughput up to 500 kSPS. The ADC128S102 has to interface to an MCU
whose supply is set at 5 V. If it is necessary to interface with an MCU that operates at 3.3 V or lower, VA and VD
will need to be separated and care must be taken to ensure that VA is powered before VD.
8.2.2 Detailed Design Procedure
The signal range requirement forces the design to use 5-V analog supply at VA, analog supply. This follows from
the fact that VA is also a reference potential for the ADC. If the requirement of interfacing to the MCU changes to
3.3-V, it will be necessary to change the VD supply voltage to 3.3 V. The maximum sampling rate of the
ADC128S102 when all channels (eight) are enabled is, Fs = F_SCLK / (16 × 8).
Note that faster sampling rates can be achieved when fewer channels are sampled. Single channel can be
sampled at the maximum rate of Fs (single) = F_SCLK / 16.
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