LM3S9792_15 Datasheet, PDF (208/1403 Pages) Texas Instruments – Stellaris LM3S9792 Microcontroller

System Control
5.2.5.2
through the specified speed of the microcontroller. The supported crystals are listed in the XTAL
bit field in the RCC register (see page 229). Note that the MOSC provides the clock source for
the USB PLL and must be connected to a crystal or an oscillator.
■ Internal 30-kHz Oscillator. The internal 30-kHz oscillator provides an operational frequency of
30 kHz ± 50%. It is intended for use during Deep-Sleep power-saving modes. This power-savings
mode benefits from reduced internal switching and also allows the MOSC to be powered down.
The internal system clock (SysClk), is derived from any of the above sources plus two others: the
output of the main internal PLL and the precision internal oscillator divided by four (4 MHz ± 1%).
The frequency of the PLL clock reference must be in the range of 3.579545 MHz to 16.384 MHz
(inclusive). Table 5-4 on page 208 shows how the various clock sources can be used in a system.
Table 5-4. Clock Source Options
Clock Source
Drive PLL?
Used as SysClk?
Precision Internal Oscillator
Yes
BYPASS = 0, OSCSRC Yes
= 0x1
BYPASS = 1, OSCSRC = 0x1
Precision Internal Oscillator divide No
-
by 4 (4 MHz ± 1%)
Yes
BYPASS = 1, OSCSRC = 0x2
Main Oscillator
Yes
BYPASS = 0, OSCSRC Yes
= 0x0
BYPASS = 1, OSCSRC = 0x0
Internal 30-kHz Oscillator
No
-
Yes
BYPASS = 1, OSCSRC = 0x3
Clock Configuration
The Run-Mode Clock Configuration (RCC) and Run-Mode Clock Configuration 2 (RCC2)
registers provide control for the system clock. The RCC2 register is provided to extend fields that
offer additional encodings over the RCC register. When used, the RCC2 register field values are
used by the logic over the corresponding field in the RCC register. In particular, RCC2 provides for
a larger assortment of clock configuration options. These registers control the following clock
functionality:
■ Source of clocks in sleep and deep-sleep modes
■ System clock derived from PLL or other clock source
■ Enabling/disabling of oscillators and PLL
■ Clock divisors
■ Crystal input selection
Important: Write the RCC register prior to writing the RCC2 register. If a subsequent write to the
RCC register is required, include another register access after writing the RCC register
and before writing the RCC2 register.
Figure 5-5 shows the logic for the main clock tree. The peripheral blocks are driven by the system
clock signal and can be individually enabled/disabled. When the PLL is enabled, the ADC clock
signal is automatically divided down to 16 MHz from the PLL output for proper ADC operation. The
PWM clock signal is a synchronous divide of the system clock to provide the PWM circuit with more
range (set with PWMDIV in RCC).
208
July 03, 2014
Texas Instruments-Production Data