TPS7A54-Q1 Datasheet, PDF (20/28 Pages) Texas Instruments – Automotive-Grade 4-A, High-Accuracy, Low-Noise, LDO Voltage Regulator

TPS7A54-Q1
SBVS312 – SEPTEMBER 2017
www.ti.com
8.1.13 Power Dissipation (P_D)
Circuit reliability demands that proper consideration be given to device power dissipation, location of the circuit
on the printed circuit board (PCB), and correct sizing of the thermal plane. The PCB area around the regulator
must be as free as possible of other heat-generating devices that cause added thermal stresses.
As a first-order approximation, power dissipation in the regulator depends on the input-to-output voltage
difference and load conditions. P_D can be calculated using Equation 5:
P_D = (V_OUT - V_IN) ´ I_OUT
(5)
NOTE
Power dissipation can be minimized, and thus greater efficiency achieved, by proper
selection of the system voltage rails. Proper selection allows the minimum input-to-output
voltage differential to be obtained. The low dropout of the TPS7A54-Q1 allows for
maximum efficiency across a wide range of output voltages.
The primary heat conduction path for the package is through the thermal pad to the PCB. Solder the thermal pad
to a copper pad area under the device. This pad area contains an array of plated vias that conduct heat to any
inner plane areas or to a bottom-side copper plane.
The maximum power dissipation determines the maximum allowable junction temperature (T_J) for the device.
Power dissipation and junction temperature are most often related by the junction-to-ambient thermal resistance
(θ_JA) of the combined PCB and device package and the temperature of the ambient air (T_A), according to
Equation 6. The equation is rearranged for output current in Equation 7.
T_J = T_A + (q_JA ´ P_D)
(6)
I_OUT = (T_J – T_A) / [θ_JA × (V_IN – V_OUT)]
(7)
Unfortunately, this thermal resistance (θ_JA) is highly dependent on the heat-spreading capability built into the
particular PCB design, and therefore varies according to the total copper area, copper weight, and location of the
planes. The θ_JA recorded in the Electrical Characteristics table is determined by the JEDEC standard, PCB, and
copper-spreading area, and is only used as a relative measure of package thermal performance. For a well-
designed thermal layout, θ_JA is actually the sum of the VQFN package junction-to-case (bottom) thermal
resistance (θ_JCbot) plus the thermal resistance contribution by the PCB copper.
8.1.14 Estimating Junction Temperature
The JEDEC standard now recommends the use of psi (Ψ) thermal metrics to estimate the junction temperatures
of the LDO when in-circuit on a typical PCB board application. These metrics are not strictly speaking thermal
resistances, but rather offer practical and relative means of estimating junction temperatures. These psi metrics
are determined to be significantly independent of the copper-spreading area. The key thermal metrics (Ψ_JT and
Ψ_JB) are given in the Electrical Characteristics table and are used in accordance with Equation 8.
Y_JT:
T
J
=
T
T
+
Y_JT
´
P
D
Y_JB:
T
J
=
T
B
+
Y_JB
´
P
D
where:
• P_D is the power dissipated as explained in Equation 5
• T_T is the temperature at the center-top of the device package, and
• T_B is the PCB surface temperature measured 1 mm from the device package and centered on the package
edge
(8)
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