TPS54362-HT_16 Datasheet, PDF (20/34 Pages) Texas Instruments – 1-A, 48-V STEP DOWN DC/DC CONVERTER WITH LOW

TPS54362-HT
SLVSBI9 – SEPTEMBER 2012
Mode Of Operation
Hysteretic Mode
Low power Mode
Active (Normal)
V_O - Lower Limit
0.82V × (R1 + R2 + R3)/(R2 + R3)
0.82V × (R1 + R2 + R3)/(R2 + R3)
VReg – tol_VReg
empty paragraph for space between the two tables
V_O – Upper limit
0.8V × (R1+R2+R3)/(R3)
VReg + tol_VReg
VReg + tol_VReg
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Comments
Min to max ripple on output
Min to max ripple on output
Min to max ripple on output
Supervisor Thresholds
Overvoltage
Reset
V_O - Typical value
0.8V × (R1 + R2 + R3)/(R3)
0.8V × (R1 + R2 + R3)/(R2 + R3)
Tolerance
± (tol_Vref + (R1 + R2/[R1 + R2 + R3]) ×
(tol_R1 + tol_R2 + tol_R3)
± (tol_Vref + (R1/[R1 + R2 + R3]) ×
(tol_R1 + tol_R2 + tol_R3)
Comments
Overvoltage threshold
setting
Reset threshold setting
Load reg/Line reg in Hysteretic Mode
This mode of operation is when a load or line transient step occurs in the application. The converter will go into a
hysteretic mode of operation until the error amplifier stabilizes and controls the output regulation to a tighter
output tolerance. During the load step the regulator upper threshold is set by the VReg_OV and the lower
threshold is set by the VReg_UV limit.
The converter enters this mode of operation during load or line transient events if the main control loop cannot
respond to regulate within the specified tolerances. The regulator exits this mode once the main control loop
responds.
Internal Undervoltage Lock Out (UVLO)
The IC is enabled on power up once the internal bandgap and bias currents are stabile, this is typically at
V_I = 3.4V (min). On power down, the internal circuitry is disabled at V_I = 2.6V (max).
Loop Control Frequency Compensation
L
VReg
C8
CESR
R4
C7
R9
C5
R6
C4
R5
VSENSE
V_ref = 0.8 V
COMP
Type 3 Compensation
Figure 17. Type 3 Compensation
Type III Compensation
fc = fsw × 0.1 (the cut off frequency, when the gain is 1 is called the unity gain frequency).
The fc is typically 1/5 to 1/10 of the switching frequency, double pole frequency response due to the LC output
filter
The modulator break frequencies as a function of the output LC filter is derived from Equation 9 and Equation 10.
The LC output filter gives a “Double Pole” which has a –180 degree phase shift
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