TCA9802 Datasheet, PDF (20/36 Pages) Texas Instruments – Level-Translating I2C Bus Buffer/Repeater

TCA9802
SCPS266 – MARCH 2017
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Typical Application (continued)
10.2.1.1 Design Requirements
The system designer must first select the correct variant of the TCA980x family for the load. In order to do this,
the information in Table 6 must be known. The setup in Figure 19 is used for these example design
requirements.
C_L is the capacitance of the bus, including the pin capacitance of each slave device connected, and the
capacitance of the board trace. It is possible to estimate the bus capacitance by summing up the pin
capacitances of each slave device on the node (using 10-pF per slave is a safe estimate, since this is the
maximum allowed per the I²C specification), but trace capacitance requires an estimation through simulation or
by getting the capacitance per unit length from the board manufacturer.
Parameter
C_L
t_r
V_CCA
V_CCB
f_SCL
Table 6. Design Requirements
Description
Load capacitance (bus capacitance) on B-
side
Rise time
VCCA supply voltage
VCCB supply voltage
I²C clock frequency
Acceptable Range
up to 400 pF
up to 300 ns
0.8 V-3.6 V
1.65 V-3.6 V
Example Value/Target
100 pF
≤ 150 ns
1.2 V
3.3 V
400 kHz
10.2.1.2 Detailed Design Procedure
Selection of the correct device is important for designers wanting optimize power consumption while transmitting.
Selecting the pull-up resistor required for the A-side is well documented already, see the I2C Bus Pullup Resistor
Calculation application report. The rest of this section deals only with selection of a device based on the B-side
design requirements.
Since the B-ports of the TCA980x family have an integrated current source, the rise time is easily calculated with
Equation 2. The graphs in the Application Curves section show the maximum capacitance load that each device
can drive (based on minimum I_CS value) to achieve a desired rise time, for different V_CCB voltages.
t_r
C_L
(0.4 uV_CCB )
I_CS
(2)
The target design requirements example is intended for 400-kHz I²C, so the appropriate selection graph to use is
Figure 22, and specifically Figure 27 since VCCB supply voltage is 3.3 V. In Figure 21, the graph has the
appropriate regions shaded to help illustrate how to select the appropriate device. When looking at the general
selection graphs, note that voltage line shifts evenly between the 1.65 V and 3.6 V traces in the general selection
graphs. For example, if VCCB in another example is 2.5 V, then the selection graph is based on a line in the
middle of the 1.65 V and the 3.6 V trace.
As shown in Figure 21, the shaded region is the appropriate region based on design requirements listed in
Table 6. Any line that touches this shaded region is able to meet the design requirements. In this example, the
TCA9803 and the TCA9802 both are able to satisfy the design requirements, since they both touch the shaded
region. The TCA9800 and the TCA9801 both fall below the shaded region. While the TCA9801 is able to meet a
rise time of about 190 ns at 100 pF (acceptable by the fast-mode rise time requirements), the design target in
this example was ≤ 150 ns. This is a consideration a system designer can make, sacrificing rise time for a lower-
power device, but in this example, the 150 ns limit is going to be upheld).
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