SN65LVDS93A-Q1 Datasheet, PDF (20/35 Pages) Texas Instruments – FlatLink Transmitter

SN65LVDS93A-Q1
SLLSEM1B – FEBRUARY 2015 – REVISED APRIL 2015
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12-bpp GPU
(See Note B)
R2 or VCC
R3 or GND
R0
R1
R2
R3(MSB)
(See Note B)
G2 or VCC
G3 or GND
G0
G1
G2
G3(MSB)
(See Note B)
B2 or VCC
B3 or GND
B0
B1
B2
B3(MSB)
HSYNC
VSYNC
ENABLE
RSVD
CLK
SN65LVDS93A-Q1
D0
D1
D2
D3
D4
D6
D27
D5
D7
D8
D9
D12
D13
D14
D10
D11
D15
D18
D19
D20
D21
D22
D16
D17
D24
D25
D26
D23
CLKIN
Y0M
Y0P
Y1M
Y1P
Y2M
Y2P
CLKOUTM
CLKOUTP
Y3M
Y3P
FPC
Cable
100
to column
driver
100
100
LVDS
timing
Controller
(6-bpc, 18-bpp)
100
to row driver
18-bpp LCD Display
(See Note A)
1.8V or 2.5V
or 3.3V
4.8k
C1
Rpullup
Rpulldown
(See Note C)
3.3V
C2
3.3V
C3
Main Board
Note A. Leave output Y3 N.C.
Note B. R3, G3, B3: this MSB of each color also connects to the 5th bit of each color for increased dynamic range of
the entire color space at the expense of none-linear step sizes between each step. For linear steps with less dynamic
range, connect D1, D8, and D18 to GND.
R2, G2, B2: these outputs also connects to the LSB of each color for increased, dynamic range of the entire color
space at the expense of none-linear step sizes between each step. For linear steps with less dynamic range, connect
D0, D7, and D15 to VCC.
Note C.Rpullup: install only to use rising edge triggered clocking.
Rpulldown: install only to use falling edge triggered clocking.
• C1: decoupling cap for the VDDIO supply; install at least 1x0.01µF.
• C2: decoupling cap for the VDD supply; install at least 1x0.1µF and 1x0.01µF.
• C3: decoupling cap for the VDDPLL and VDDLVDS supply; install at least 1x0.1µF and 1x0.01µF.
Figure 17. 12-Bit Color Host to 18-Bit Color LCD Panel Display Application
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