LP8758-E0_16 Datasheet, PDF (20/61 Pages) Texas Instruments – Four-Output Synchronous Step-Down DC-DC Converter

LP8758-E0
SNVSAC6A – JANUARY 2016 – REVISED JANUARY 2016
www.ti.com
Table 2. Summary of Interrupt Signals
EVENT
RESULT
INTERRUPT REGISTER
AND BIT
INTERRUPT MASK
STATUS BIT
RECOVERY /
INTERRUPT CLEAR
Current limit
triggered (20 µs
debounce)
No effect
INT_TOP.INT_BUCKx = 1
INT_BUCKx.BUCKx_ILIM_I
NT = 1
BUCKx_MASK.BUCKx_ILI
M_MASK
BUCKx_STAT.BUCKx_IL
IM_STAT
Write 1 to
INT_BUCKx.BUCKx_ILI
M_INT bit
Interrupt is not cleared if
current limit is active
Short circuit (V_OUT < Converter core
INT_TOP.INT_BUCKx = 1
N/A
0.35 V at 1 ms after disable
INT_BUCK_0_1.BUCKx_SC
enable) or Overload
_INT = 1
(V_OUT decreasing
below 0.35V during
or
INT_BUCK_2_3.BUCKx_SC
operation, 1 ms
_INT = 1
debounce)
N/A
Write 1 to
INT_BUCK_0_1.BUCKx_
SC_INT or
to
INT_BUCK_2_3.BUCKx_
SC_INTbit
Thermal Warning No effect
INT_TOP.TDIE_WARN = 1
TOP_MASK.TDIE_WARN
_MASK
TOP_STAT.TDIE_WARN
_STAT
Write 1 to
INT_TOP.TDIE_WARN
bit
Interrupt is not cleared if
temperature is above
thermal warning level
Thermal Shutdown All converter cores
disabled
INT_TOP.TDIE_SD = 1
N/A
TOP_STAT.TDIE_SD_S Write 1 to
TAT
INT_TOP.TDIE_SD bit
Interrupt is not cleared if
temperature is above
thermal shutdown level
Powergood, output No effect
voltage reaches the
programmed value
INT_TOP.INT_BUCKx = 1
INT_BUCK_0_1.BUCKx_PG
_INT = 1
or
INT_BUCK_2_3.BUCKx_PG
_INT = 1
BUCK_0_1_MASK.BUCKx
_PG_MASK
BUCK_2_3_MASK.BUCKx
_PG_MASK
BUCK_0_1_STAT.BUCK
x_PG_STAT
BUCK_2_3_STAT.BUCK
x_PG_STAT
Write 1 to
INT_BUCK_0_1.BUCKx_
PG_INT bit
or to
INT_BUCK_2_3.BUCKx_
PG_INT bit
Load current
No effect
measurement ready
INT_TOP.I_LOAD_READY TOP_MASK.I_LOAD_REA
N/A
Write 1 to
=1
DY_MASK
INT_TOP.I_LOAD_REA
DY bit
Start-up (NRST
Device ready for
INT_TOP.RESET_REG = 1 TOP_MASK.RESET_REG
N/A
Write 1 to
rising edge)
operation, registers
_MASK
INT_TOP.RESET_REG
reset to default values
bit
Glitch on supply
Immediate shutdown INT_TOP.RESET_REG = 1 TOP_MASK.RESET_REG
N/A
Write 1 to
voltage and UVLO followed by powerup,
_MASK
INT_TOP.RESET_REG
triggered (VANA
registers reset to
bit
falling and rising) default values
Software requested Immediate shutdown INT_TOP.RESET_REG = 1 TOP_MASK.RESET_REG
N/A
Write 1 to
reset
followed by powerup,
_MASK
INT_TOP.RESET_REG
registers reset to
bit
default values
7.3.5.1 Warnings for Diagnosis (Interrupt)
7.3.5.1.1 Output Current Limit
The converter cores have programmable output peak current limits. The limits are individually programmed for all
buck converter cores with BUCKx_CTRL2.ILIMx[2:0] bits. If the load current is increased so that the current limit
is triggered, the regulator continues to regulate to the limit current level (current peak regulation). The voltage
may decrease if the load current is higher than limit current. If the current regulation continues for 20 µs, the
LP8758-E0 device sets the INT_BUCKx.BUCKx_ILIM_INT bit and pulls the nINT pin low. The host processor can
read BUCKx_STAT.BUCKx_ILIM_STAT bits to see if the converter cores is still in peak current regulation mode.
For example, if the load on Buck0 output is so high that the output voltage V_OUT decreases below a 350-mV
level, the LP8758-E0 device disables the converter core Buck0 and sets the INT_BUCK_0_1.BUCK0_SC_INT
bit. In addition the BUCK_0_1_STAT.BUCK0_STAT bit is set to 0. The interrupt is cleared when the host
processor writes 1 to INT_BUCK_0_1.BUCK0_SC_INT bit. The overload situation is shown in Figure 11.
20
Submit Documentation Feedback
Product Folder Links: LP8758-E0
Copyright © 2016, Texas Instruments Incorporated