LM4931 Datasheet, PDF (20/50 Pages) National Semiconductor (TI) – Audio Subsystem with Mono High Efficiency Loudspeaker and Stereo Headphone Amplifiers

LM4931
SNAS251E – APRIL 2004 – REVISED MAY 2013
Digital Interface Configuration Registers
This register is used to control the format of the PCM, I2S, and GPIO interfaces.
DATA BIT
DEFAULT
Table 21. DEFAULT CHART FOR INTERFACES (09h)
7
6
5
4
3
2
0
0
0
0
0
0
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1
0
0
0
Table 22. INTERFACES (09h) (SET = LOGIC 1, CLEAR = LOGIC 0)
Address
0
1
2
3
4
5
6
7
Register
PCM_COMPANDED
PCM_ALAW_ULAW
PCM_MS
PCM_LONG
I²S_MS
I²S_RES
RSVD
RSVD
Description
If set the data is assumed to be in either A-law or u-law 8-
bit companded form, otherwise it is assumed to be up to 16
bits of MSB first linear 2’s complement PCM format⁽¹⁾.
If set the data is assumed to be A-law, otherwise it is u-law
companded ⁽¹⁾.
When set the PCM operates in a master mode.
When set the PCM operates in long mode⁽¹⁾.
When set the I²S operates in a master mode.
This selects if each word is 16 or 32 bits long⁽²⁾:
I²S_RES
Word Length
0
16
1
32
In 32 bit mode the 18 MSBs are passed to the DAC. In 16
bit mode all 16 bits are passed to the DAC.
RESERVED ⁽³⁾
RESERVED ⁽³⁾
(1) It is recommended to alter this bit only while the part is in Powerdown mode.
(2) Always operate the digital IO at the lowest frequency possible to save power and reduce noise. Obviously this can limit the resolution of
the I²S interface from 18 bits to 16 bits, but if only 16 bit data is available use the 16 bit mode to reduce I/O power.
(3) Reserved bits should be set to zero when programming the associated register.
Power Management Configuration Registers
This register is used to control the power management settings.
Table 23. DEFAULT CHART FOR PMC_CONFIG (0Ah)
DATA BIT
7
6
5
4
3
2
1
0
DEFAULT
0
0
0
0
0
0
0
0
Address
0
2:1
Table 24. PMC_CONFIG (0Ah) (SET = LOGIC 1, CLEAR = LOGIC 0)
Register
ZXD_DISABLE
CAP_SIZE
Description
If set then zero cross detection is ignored when changing modes or gains⁽¹⁾.
Set to accommodate a selected bypass capacitor value to give correct turn-on
delay and click/pop performance. Value is set as follows⁽²⁾:
2:1
Delay
Capacitor Size/Time
00
short
0.1μF/25ms
01
medium
1μF/100ms
10
long
2.2μF/200ms
11
test
Test Mode/1ms
(1) To ensure a successful transition into Powerdown Mode, ZXD_DISABLE must be set whenever there is no audio input signal present.
(2) The effect of CAP_SIZE will vary with the audio clock frequency. The delays quoted are for a 12.288MHz MCLK. These will scale
inversely to the MCLK frequency. For example if used in a 44.1kHz application where the PLL output is 11.2896MHz, “01” or 100ms will
be 100ms*11.2896/12.288 = 108.8ms. It is suggested that to save power earlier during the shutdown cycle, the PLL can be disabled and
the MCLK or MCLK/2 can be used to bypass the PLL and also provide longer shutdown times for further reduced click and pop.
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