DAC121C081_16 Datasheet, PDF (20/41 Pages) Texas Instruments – 12-Bit Micro Power Digital-to-Analog Converter

DAC121C081, DAC121C085
SNAS395E – DECEMBER 2007 – REVISED JANUARY 2016
www.ti.com
The t_outz specification is typically 87 ns in Standard-Fast Mode and 38 ns in Hs-Mode.
8.4 Device Functional Modes
8.4.1 Power-Down Modes
The DAC121C081 has three power-down modes. In power-down mode, the supply current drops to 0.13 µA at 3
V and 0.15 µA at 5 V (typical). The DAC121C081 is put into power-down mode by writing a one to PD1 and/or
PD0. The outputs can be set to high impedance, terminated by 2.5 kΩ to GND, or terminated by 100 kΩ to GND
(see Figure 26).
The bias generator, output amplifier, resistor string, and other linear circuitry are all shut down in any of the
power-down modes. When the DAC121C081 is powered down, the value written to the DAC register, including
the power-down bits, is saved. While the DAC is in power-down, the saved DAC register contents can be read
back. When the DAC is brought out of power-down mode, the DAC register contents will be overwritten and V_OUT
will be updated with the new 12-bit data value.
The time to exit power-down (Wake-Up Time) is typically 0.8 µs at 3 V and 0.5 µs at 5 V.
8.5 Programming
8.5.1 Writing to the DAC Register
To write to the DAC, the master addresses the part with the correct slave address (A6-A0) and writes a zero to
the read/write bit. If addressed correctly, the DAC returns an ACK to the master. The master then sends out the
upper data byte. The DAC responds by sending an ACK to the master. Next, the master sends the lower data
byte to the DAC. The DAC responds by sending an ACK again. At this point, the master either sends the upper
byte of the next data word to be converted by the DAC, generates a Stop condition to end communication, or
generates a Repeated Start condition to begin communication with another device on the bus. Until generating a
Stop condition, the master can continuously write the upper and lower data bytes to the DAC register. This
allows for a maximum DAC conversion rate of 188.9 kilo-conversions per second in Hs-mode.
1
91
91
9
SCL
SDA
A6 A5 A4 A3 A2 A1 A0 R/W
0 0 PD1 PD0 D11 D10 D9 D8
D7 D6 D5 D4 D3 D2 D1 D0
Start by
ACK
ACK
ACK Stop by
Master
Frame 1
Address Byte
from Master
by
DAC121C081
Frame 2
Data Byte from
Master
by
DAC121C081
Frame 3
Data Byte from
Master
by Master
DAC121C081
Repeat Frames
2 & 3 for
Continuous Mode
Figure 24. Typical Write to the DAC Register
8.5.2 Reading from the DAC Register
To read from the DAC register, the master addresses the part with the correct slave address (A6-A0) and writes
a one to the read/write bit. If addressed correctly, the DAC returns an ACK to the master. Next, the DAC sends
out the upper data byte. The master responds by sending an ACK to the DAC to indicate that it wants to receive
another data byte. Then the DAC sends the lower data byte to the master. Assuming only one 16-bit data word is
read, the master sends a NACK after receiving the lower data byte. At this point, the master either generates a
Stop condition to end communication, or a Repeated Start condition to begin communication with another device
on the bus.
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