CDCM7005-SP Datasheet, PDF (20/41 Pages) Texas Instruments – 3.3-V HIGH PERFORMANCE RAD-TOLERANT CLASS V, CLOCK SYNCHRONIZER AND JITTER CLEANER

CDCM7005-SP
SGLS390E – JULY 2009 – REVISED AUGUST 2012
Word 1
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BIT
BIT NAME
DESCRIPTION/FUNCTION
0
C0
Register Selection
1
C1
Register Selection
2
OUTSEL0 Output (Yx) Signaling For Output Y0A, Y0B:
Selection
LVPECL = enabled [1]; LVCMOS = enabled [0];
3
OUTSEL1
For Outputs Y1A, Y1B:
LVPECL = enabled [1]; LVCMOS = enabled [0];
4
OUTSEL2
For Outputs Y2A, Y2B:
LVPECL = enabled [1]; LVCMOS = enabled [0];
5
OUTSEL3
For Outputs Y3A, Y3B:
LVPECL = enabled [1]; LVCMOS = enabled [0];
6
OUTSEL4
For Outputs Y4A, Y4B:
LVPECL = enabled [1]; LVCMOS = enabled [0];
7
OUT0A0
Output Y0 Mode
Output Y0A Mode Bit 0
8
OUT0A1
Output Y0A Mode Bit 1
9
OUT0B0
Output Y0B Mode Bit 0
10 OUT0B1
Output Y0B Mode Bit 1
11 OUT1A0
Output Y1 Mode
Output Y1A Mode Bit 0
12 OUT1A1
Output Y1A Mode Bit 1
13 OUT1B0
Output Y1B Mode Bit 0
14 OUT1B1
Output Y1B Mode Bit 1
15 OUT2A0
Output Y2 Mode
Output Y2A Mode Bit 0
16 OUT2A1
Output Y2A Mode Bit 1
17 OUT2B0
Output Y2B Mode Bit 0
18 OUT2B1
Output Y2B Mode Bit 1
19 OUT3A0
Output Y3 Mode
Output Y3A Mode Bit 0
20 OUT3A1
Output Y3A Mode Bit 1
21 OUT3B0
Output Y3B Mode Bit 0
22 OUT3B1
Output Y3B Mode Bit 1
23 OUT4A0
Output Y4 Mode
Output Y4A Mode Bit 0
24 OUT4A1
Output Y4A Mode Bit 1
25 OUT4B0
Output Y4B Mode Bit 0
26 OUT4B1
Output Y4B Mode Bit 1
27 SREF
Status Ref.
Displays the status of the reference clock at the
STATUS_REF output [0]
Displays the selected clock (high for PRI_REF
and low for SEC_REF clock) at the
STATUS_REF
output [1]
28 SXOIREF Status VCXO or
I_REF_CP
Selects STATUS_VCXO [0]
Selects I_REF_CP [1] which enable external
reference resistor used for charge pump
current and analog PLL lock detect output
current.
29 ADLOCK
Analog or Digital Lock Selects Digital PLL_LOCK [0]
Selects Analog PLL_LOCK [1]
30 90DIV4
90 degree shift div-4 90 degree output phase shift in div-4 mode
on [1]; off [0]⁽¹⁾
31 90DIV8
90 degree shift div-8 90 degree output phase shift in div-8 mode
on [1]; off [0]⁽¹⁾
POWER UP
CONDITION
1
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PINS AFFECTED
24, 25
29, 30
33, 34
37, 38
42, 43
24
24
25
25
29
29
30
30
33
33
34
34
37
37
38
38
42
42
43
43
50
49, 52
52
Yx
Yx
(1) The P 16-Div has to be selected to obtain the 90 degree phase shift. If bit 30 or bit 31 is set, the Div-by-16 mode is no longer available.
The outputs are switched in pairs. Only one bit can be set at a time. If both bits set to [1] at the same time, no 90 degree phase shift
mode is selected (equal to off-mode setting).
20
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