ADS8519_14 Datasheet, PDF (20/29 Pages) Texas Instruments – 16-Bit, 250kSPS, Serial, CMOS, Sampling ANALOG-TO-DIGITAL CONVERTER

ADS8519
SLAS462D – JUNE 2007 – REVISED SEPTEMBER 2010
www.ti.com
Neither the internal reference nor the buffer should be used to drive an external load. Such loading can degrade
performance. Any load on the internal reference causes a voltage drop across the 4kΩ resistor and affects gain.
The internal buffer is capable of driving ±2mA loads, but any load can cause perturbations of the reference at the
CDAC, degrading performance. It should be pointed out that, unlike other devices with a similar input structure,
the ADS8519 does not require a second high-speed amplifier used as a buffer to isolate the CAP pin from the
signal-dependent current in the R3_IN pin, but can tolerate it if one does exist.
The external reference voltage can vary from 3.9V to 4.2V. The reference voltage determines the size of the
least significant bit (LSB). The larger reference voltages produce a larger LSB, which can improve SNR. Smaller
reference voltages can degrade SNR.
2.2mF
+15 V
22pF
2kW
100nF
Pin 7
2kW
Pin 1
V_IN
Pin 2
OPA627
Pin 6
22pF
or
OPA132
Pin 3
Pin 4
2.2mF
100nF
ADS8519
2.2mF
R1_IN
AGND1
R2_IN
R3_IN
CAP
REF
2.2mF
AGND2
GND
GND
-15 V
GND GND GND GND GND
Figure 31. Typical Driving Circuitry (±10V, No Trim)
SPECIFIC FUNCTION
Initiate conversion and
output data using internal
clock
Initiate conversion and
output data using external
clock
No actions
Power down
Selecting output format
CS
1>0
0
1>0
0
R/C
0
1>0
0
1>0
BUSY
1
1
1
1
1>0 1
1
1>0
0
0
1
0>1
0
0
0
0>1
x
x
x
x
x
x
x
x
x
x
x
x
Table 3. Control Truth Table
EXT/INT
0
0
1
1
1
1
1
x
x
x
x
x
DATACLK
Output
Output
Input
Input
Input
Input
Input
x
x
x
x
x
PWRD
0
0
0
0
x
0
0
0
0
1
x
x
SB/BTC
x
x
x
x
x
x
x
x
x
x
0
1
OPERATION
Initiates conversion n. Data from conversion n - 1
clocked out on DATA synchronized to 16 clock
pulses output on DATACLK.
Initiates conversion n.
Initiates conversion n.
Outputs data with or without SYNC pulse. See the
Reading Data section.
Outputs data with or without SYNC pulse. See
Reading Data section.
This is an acceptable condition.
Analog circuitry powered. Conversion can
proceed..
Analog circuitry disabled. Data from previous
conversion maintained in output registers.
Serial data are output in binary twos complement
format.
Serial data are output in straight binary format.
20
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