ADS7042 Datasheet, PDF (20/43 Pages) Texas Instruments – Ultra-Low Power, Ultra-Small Size, 12-Bit, 1-MSPS, SAR ADC

ADS7042
SBAS608C – JUNE 2014 – REVISED DECEMBER 2015
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8.4 Device Functional Modes
8.4.1 Offset Calibration
The ADS7042 includes a feature to calibrate the device internal offset. During offset calibration, the analog input
pins (AINP and AINM) are disconnected from the sampling stage. The device includes an internal offset
calibration register (OCR) that stores the offset calibration result. The OCR is an internal register and cannot be
accessed by the user through the serial interface. The OCR is reset to zero on power-up. Therefore, TI
recommends calibrating the offset on power-up to bring the offset within the specified limits. If the operating
temperature or analog supply voltage reflect a significant change, the offset can be recalibrated during normal
operation. Figure 35 shows the offset calibration process.
Device
Power Up
(4)
Power ^Recycle
First ^{Serlieasl sTrtSahnaDsnOfe1=r6F0SrxaC0mL0Ke0swith}
Normal Operation
With Uncalibarted
offset
Data Capture⁽¹⁾
CaliSbrDaOtio=n _{0oxn0P0o0wer Up (3:)}
Power _{Recycle (4)}
Normal Operation
With Calibarted
offset
Data Capture⁽¹⁾
Calibration during Normal Operation⁽²⁾
(1) See the Timing Characteristics section for timing specifications.
(2) See the Offset Calibration During Normal Operation section for details.
(3) See the Offset Calibration on Power-Up section for details.
(4) The power recycle on the AVDD supply is required to reset the offset calibration and to bring the device to a power-up
state.
Figure 35. Offset Calibration
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