ADS7041_15 Datasheet, PDF (20/42 Pages) Texas Instruments – Ultra-Low Power, Ultra-Small Size, 10-Bit, 1-MSPS, SAR ADC

ADS7041
SBAS675C – NOVEMBER 2014 – REVISED DECEMBER 2015
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Device Functional Modes (continued)
8.4.1.1 Offset Calibration on Power-Up
The device initiates offset calibration on the first CS falling edge after power-up and calibration completes if the
CS pin remains low for at least 16 SCLK falling edges after the first CS falling edge. The SDO output remains
low during calibration. The minimum acquisition time must be provided after calibration for acquiring the first
sample. If the device is not provided with at least 16 SCLKs during the first serial transfer frame after power-up,
the OCR is not updated. Table 2 provides the timing parameters for offset calibration on power-up.
For subsequent samples, the device adjusts the conversion results with the value stored in the OCR. The
conversion result adjusted with the value stored in OCR is provided by the device on the SDO output. Figure 37
shows the timing diagram for offset calibration on power-up.
Table 2. Offset Calibration on Power-Up
f_CLK-CAL
f_CLK-CAL
t_POWERUP-CAL
t_ACQ
t_{PH_CS}
t_{SU_CSCK}
t_{D_CKCS}
SCLK frequency for calibration for 2.25 V < AVDD < 3.6 V
SCLK frequency for calibration for 1.65 V < AVDD < 2.25 V
Calibration time at power-up
Acquisition time
CS high time
Setup time: CS falling to SCLK falling
Delay time: last SCLK falling to CS rising
MIN
15 t_SCLK
235
t_ACQ
15
10
TYP
MAX
14
12
UNIT
MHz
MHz
ns
ns
ns
ns
ns
Start
Power-up
Calibration
t_POWERUP-CAL
t_{PH_CS}
t_ACQ
Sample
#1
CS
t_{SU_CSCK}
t_{D_CKCS}
SCLK(f_CLK-CAL)
1
2
15 16
SDO
Figure 37. Offset Calibration on Power-Up Timing Diagram
20
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