ADS5403 Datasheet, PDF (20/44 Pages) Texas Instruments – Single Channel 12-Bit 500Msps Analog to Digital Converter

ADS5403
SLAS944B – FEBRUARY 2013 – REVISED JANUARY 2014
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POWER DOWN MODES
The ADS5403 can be configured via SPI write (address x37) to a stand-by, light or deep sleep power mode
which is controlled by the ENABLE pin. The sleep modes are active when the ENABLE pin goes low. Different
internal functions stay powered up which results in different power consumption and wake up time between the
two sleep modes.
Sleep mode
Complete Shut Down
Stand-by
Deep Sleep
Light Sleep
Wake up time
2.5 ms
100µs
20µs
2µs
Power Consumption Auto
correction disabled
7mW
7mW
220mW
367mW
Power Consumption Auto
correction enabled
7mW
7mW
305mW
448mW
TEST PATTERN OUTPUT
The ADS5403 can be configured to output different test patterns that can be used to verify the digital interface is
connected and working properly. To enable the test pattern mode, the high performance mode 1 has to be
disabled first via SPI register write. Then different test patterns can be selected by configuring registers x3C, x3D
and x3E. All three registers must be configured for the test pattern to work properly.
First set HP1 = 0 (Addr 0x01, D01)
Register Address
0x3C
0x3D
0x3E
All 0s
0x8000
0x0000
0x0000
All 1s
0xBFFC
0x3FFC
0x3FFC
Toggle (0xAAA => 0x555)
0x9554
0x2AA8
0x1554
Toggle (0xFFF => 0x000)
0xBFFC
0x0000
0x3FFC
Register
Address
Custom Pattern
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
x3C
1
0
0
0
x3D
0
0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0
0
x3E
0
0
0
0
For normal operation, set HP1 = 1 (Addr 0x01, D01) and 0x3C, 0x3D, 0x3E all to 0.
CLOCK INPUT
The ADS5403 clock input can be driven differentially with a sine wave, LVPECL or LVDS source with little or no
difference in performance. The common mode voltage of the clock input is set to 0.9V using internal 2kΩ
resistors. This allows for AC coupling of the clock inputs. The termination resistors should be placed as close as
possible to the clock inputs in order to minimize signal reflections and jitter degradation.
CLKINP
CLKINN
0.1uF
2kΩ
0.9V
2kΩ
CLKINP
RT
0.1uF
RT
CLKINN
0.1uF
Recommended differential clock driving circuit
Figure 35. Recommended Differential Clock Driving Circuit
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