TPS7A4201 Datasheet, PDF (2/19 Pages) Texas Instruments – 28-V Input Voltage, 50-mA Voltage Regulator

TPS7A42
SBVS184 – DECEMBER 2011
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PRODUCT
TPS7A4201 yyy z
ORDERING INFORMATION⁽¹⁾
YYY is package designator.
Z is package quantity.
V_OUT
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the
device product folder on www.ti.com.
ABSOLUTE MAXIMUM RATINGS⁽¹⁾
Over operating free-air temperature range (unless otherwise noted).
Voltage
Current
Temperature
Electrostatic discharge rating
IN pin to GND pin
OUT pin to GND pin
OUT pin to IN pin
FB pin to GND pin
FB pin to IN pin
EN pin to IN pin
EN pin to GND pin
Peak output
Operating virtual junction, T_J
Storage, T_stg
Human body model (HBM)
Charged device model (CDM)
VALUE
MIN
MAX
–0.3
+30
–0.3
+30
–30
+0.3
–0.3
+2
–30
+0.3
–30
0.3
–0.3
+30
Internally limited
–40
+125
–65
+150
2.5
500
UNIT
V
V
V
V
V
V
°C
°C
kV
V
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to
absolute-maximum rated conditions for extended periods may affect device reliability.
THERMAL INFORMATION
THERMAL METRIC⁽¹⁾
TPS7A42
DGN (MSOP)
UNITS
8 PINS
θ_JA
θ_JC(top)
θ_JB
ψ_JT
ψ_JB
θ_JC(bottom)
Junction-to-ambient thermal resistance
Junction-to-case(top) thermal resistance
Junction-to-board thermal resistance
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case(bottom) thermal resistance
66.7
54.1
38.1
°C/W
2.0
37.8
15.5
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
DISSIPATION RATINGS
BOARD
High-K ⁽¹⁾
PACKAGE
DGN
R_θJA
55.9°C/W
R_θJC
8.47°C/W
DERATING FACTOR
ABOVE T_A = +25°C
16.6mW/°C
T_A ≤ +25°C POWER
RATING
1.83W
T_A = +70°C POWER
RATING
1.08W
T_A = +85°C POWER
RATING
0.833W
(1) The JEDEC High-K (2s2p) board design used to derive this data was a 3-inch x 3-inch multilayer board with 2-ounce internal power and
ground planes and 2-ounce copper traces on top and bottom of the board.
2
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