TPS72301-Q1 Datasheet, PDF (2/16 Pages) Texas Instruments – 200 mA Low-Noise, High-PSRR Negative Output Low-Dropout Linear Regulators

TPS72301-Q1
TPS72325-Q1
SLVSAJ4A – SEPTEMBER 2010 – REVISED MARCH 2011
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PRODUCT
TPS72301QDBVRQ1
TPS72325QDBVRQ1
ORDERING INFORMATION^{(1) (2)}
V_OUT ⁽²⁾
adjustable output voltage
nominal output voltage = 2.5V
TOP-SIDE MARKING
PPHQ
PSBQ
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Output voltages from –1.2V to –9V in 100mV increments are available. Minimum order quantities apply; contact factory for details and
availability.
ABSOLUTE MAXIMUM RATINGS^{(1) (2)}
Over operating temperature range, unless otherwise noted.
Input voltage range, V_IN
Noise reduction pin voltage range, V_NR
Enable voltage range, V_EN
Output current, I_OUT
Output short-circuit duration
Continuous total power dissipation, P_D
Junction temperature range, T_J
Storage temperature range, T_stg
Latch-up performance meets 100 mA per AEC-Q100 | Class I
Human-Body Model
ESD ratings
Machine Model
Charged-Device Model
VALUE
–11 to +0.3
–11 to +5.5
–V_IN to +5.5
Internally limited
Indefinite
See Power Dissipation Ratings table
–55 to +150
–65 to +150
100
2000
200
500
UNITS
V
V
V
°C
°C
mA
kV
V
V
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
POWER DISSIPATION RATINGS
BOARD
Low-K ⁽¹⁾
High-K ⁽²⁾
PACKAGE
DBV
DBV
R_θJC
64°C/W
64°C/W
R_θJA
255°C/W
180°C/W
DERATING FACTOR
ABOVE T_A = +25°c
3.9mW/°C
5.6mW/°C
T_A ≤ +25°c
POWER
RATING
390mW
560mW
T_A = +70°c
POWER
RATING
215mW
310mW
T_A = +85°c
POWER
RATING
155mW
225mW
(1) The JEDEC Low-K (1s) board design used to derive this data was a 3 inch × 3 inch, two-layer board with 2-ounce copper traces on top
of the board.
(2) The JEDEC High-K (2s2p) board design used to derive this data was a 3 inch × 3 inch, multilayer board with 1-ounce internal power and
ground planes and 2-ounce copper traces on the top and bottom of the board.
2
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