TPS71433DCKR Datasheet, PDF (2/19 Pages) Texas Instruments – 80mA, 10V, 3.2muA Quiescent Current LOW-DROPOUT LINEAR REGULATOR

TPS714xx
SBVS116C – DECEMBER 2008 – REVISED MARCH 2011
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PRODUCT
TPS714xxyyyz
AVAILABLE OPTIONS⁽¹⁾
V_OUT ⁽²⁾
XX is nominal output voltage (for example 33 = 3.3V, 01 = Adjustable)
YYY is Package Designator
Z is Package Quantity
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Custom output voltages are available on a quick-turn basis for prototyping. Production quantities are available; minimum package order
quantities apply. Contact factory for details and availability.
ABSOLUTE MAXIMUM RATINGS
Over operating temperature range, unless otherwise noted.⁽¹⁾
PARAMETER
V_IN range
V_OUT range
V _{FB range}
Peak output current
Continuous total power dissipation
Junction temperature range, T_J
Storage temperature range
ESD rating
Human body model (HBM)
Charged device model (CDM)
TPS714xx
UNIT
–0.3 to +24
V
- 0.3 to +9.9
V
-0.3 to +4
V
Internally limited
See Power Dissipation Rating table
–40 to +125
°C
–65 to +150
°C
2
kV
500
V
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
POWER DISSIPATION RATING TABLE
BOARD
High-K ⁽¹⁾
High-K ⁽¹⁾
PACKAGE
DCK
DRV
R_θJA°C/W
315
65
DERATING FACTOR
ABOVE T_A = +25°C
3.18mW/°C
15.4mW/°C
T_A ≤ 25°C POWER
RATING
320mW
1.54W
T_A = +70°C POWER T_A = +85°C POWER
RATING
RATING
175mW
100mW
850mW
0.62W
(1) The JEDEC High-K (2s2p) board design used to derive this data was a 3 inch × 3 inch, multilayer board with 1-ounce internal power and
ground planes and 2-ounce copper traces on top and bottom of the board.
2
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