TPS54611 Datasheet, PDF (2/24 Pages) Texas Instruments – 3-V TO 6-V INPUT, 6-A OUTPUT SYNCHRONOUS BUCK PWM SWITCHER WITH INTEGRATED FETs (SWIFT™)

TPS54611, TPS54612
TPS54613, TPS54614
TPS54615, TPS54616
SLVS400C − AUGUST 2001 − REVISED APRIL 2005
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during
storage or handling to prevent electrostatic damage to the MOS gates.
PWP PACKAGE
(TOP VIEW)
AGND
VSENSE
NC
PWRGD
BOOT
PH
PH
PH
PH
PH
PH
PH
PH
PH
1
28
2
27
3
26
4
25
5
24
6
23
7 THERMAL 22
8
PAD ₂₁
9
20
10
19
11
18
12
17
13
16
14
15
RT
FSEL
SS/ENA
VBIAS
VIN
VIN
VIN
VIN
VIN
PGND
PGND
PGND
PGND
PGND
AVAILABLE OPTIONS
PACKAGED DEVICES
PACKAGED DEVICES
T_A
OUTPUT
VOLTAGE
PLASTIC HTSSOP
(PWP^)(1)(2)
T_A
OUTPUT
VOLTAGE
PLASTIC HTSSOP
(PWP^)(1)(2)
0.9 V
TPS54611PWP
1.8 V
TPS54614PWP
−40°C to 85°C
1.2 V
TPS54612PWP
−40°C to 85°C
2.5 V
TPS54615PWP
1.5 V
TPS54613PWP
3.3 V
TPS54616PWP
(1) _{For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI}
website at www.ti.com.
(2) _{The PWP package is also available taped and reeled. Add an R suffix to the device type (i.e., TPS54616PWPR). See the application section}
of this data sheet for PowerPAD drawing and layout information.
Terminal Functions
TERMINAL
NAME
NO.
DESCRIPTION
AGND
1 Analog ground. Return for slow-start capacitor, VBIAS capacitor, RT resistor FSEL. Make PowerPAD connection to AGND.
BOOT
5 Bootstrap input. 0.022-µF to 0.1-µF low-ESR capacitor connected from BOOT to PH generates floating drive for the
high-set FET driver.
NC
3 No connection
PGND
15−19 Power ground. High current return for the low-side driver and power MOSFET. Connect PGND with large copper areas to
the input and output supply returns, and negative terminals of the input and output capacitors.
PH
6−14 Phase input/output. Junction of the internal high-side and low-side power MOSFETs, and output inductor.
PWRGD
4 Power good open drain output. High-Z when VSENSE ≥ 90% V_ref, otherwise PWRGD is low. Note that output is low when
SS/ENA is low or internal shutdown signal active.
RT
28 Frequency setting resistor input. Connect a resistor from RT to AGND to set the switching frequency.
SS/ENA
26 Slow-start/enable input/output. Dual function pin which provides logic input to enable/disable device operation and
capacitor input to externally set the start-up time.
FSEL
27 Frequency select input. Provides logic input to select between two internally set switching frequencies.
VBIAS
25 Internal bias regulator output. Supplies regulated voltage to internal circuitry. Bypass VBIAS pin to AGND pin with a high
quality, low-ESR 0.1-µF to 1-µF ceramic capacitor.
VIN
20−24 Input supply for the power MOSFET switches and internal bias regulator. Bypass VIN pins to PGND pins close to device
package with a high quality, low-ESR 1-µF to 10-µF ceramic capacitor.
VSENSE
2 Error amplifier inverting input. Connect directly to output voltage sense point.
2