TMS320F28PLC83 Datasheet, PDF (2/6 Pages) Texas Instruments – TMS320F28PLC83 Power Line Communication (PLC) Microcontroller Technical Brief

TMS320F28PLC83
SPRT701 – JUNE 2014
1.4 Functional Block Diagram
M0 SARAM (1Kx16)
(0-wait, Non-Secure)
M1 SARAM (1Kx16)
(0-wait, Non-Secure)
L5 DPSARAM (8Kx16)
(0-wait, Non-Secure)
DMA RAM0
L6 DPSARAM (8Kx16)
(0-wait, Non-Secure)
DMA RAM1
L7 DPSARAM (8Kx16)
(0-wait, Non-Secure)
DMA RAM2
L8 DPSARAM (8Kx16)
(0-wait, Non-Secure)
DMA RAM3
DMA Bus
COMP1OUT
COMP2OUT
COMP3OUT
COMP
+
DAC
A[1:0]
B[1:0]
ADC
0-wait
Result
Regs
ADC
16-bit Peripheral Bus
SCI-A/B SPI-A/B _I2C-A
(4L FIFO) (4L FIFO) _{(4L FIFO)}
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L0 DPSARAM (2Kx16)
(0-wait, Secure)
L1 DPSARAM (1Kx16)
(0-wait, Secure)
L2 DPSARAM (1Kx16)
(0-wait, Secure)
L3 DPSARAM (4Kx16)
(0-wait, Secure)
L4 SARAM (8Kx16)
(0-wait, Secure)
OTP 1Kx16
Secure
Code
Security
Module
(CSM)
FLASH
128Kx16
8 equal sectors
Secure
PUMP
PSWD
OTP/Flash
Wrapper
Memory Bus
Boot-ROM
(32Kx16)
(0-wait,
Non-Secure)
C28x 32-bit CPU
VCU
DMA
6-ch
OSC1, OSC2,
Ext, PLLs,
LPM, WD,
CPU Timers0/1/2,
PIE
TRST
TCK, TDI, TMS
TDO
XCLKIN
LPM Wakeup
3 Ext. Interrupts
X1
X2
XRS
DMA Bus
Memory Bus
32-bit Peripheral Bus
ePWM1, ePWM2
HRPWM (2 ch)
32-bit Peripheral
Bus
McBSP-A
32-bit Peripheral
Bus
eCAP-1
GPIO Mux
A. Not all peripheral pins are available at the same time due to multiplexing.
Figure 1-1. Functional Block Diagram
1.5 Trademarks
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2
Introduction
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