TLK1201RCP Datasheet, PDF (2/25 Pages) Texas Instruments – ETHERNET TRANSCEIVERS

TLK1201RCP, TLK1201IRCP
ETHERNET TRANSCEIVERS
SLLS506E − AUGUST 2001 − REVISED MAY 2007
description (continued)
The primary application of this device is to provide building blocks for point-to-point baseband data transmission
over controlled impedance media of 50 Ω or 75 Ω. The transmission media can be printed-circuit board traces,
copper cables, or fiber-optical media. The ultimate rate and distance of data transfer is dependent upon the
attenuation characteristics of the media and the noise coupling to the environment.
The TLK1201I performs the data serialization, deserialization, and clock extraction functions for a physical layer
interface device. The transceiver operates at 1.25 Gbps (typical), providing up to 1 Gbps of data bandwidth over
a copper or optical media interface.
The TLK1201I supports both the defined 10-bit interface (TBI) and a reduced 5-bit interface utilizing double data
rate (DDR) clocking. In the TBI mode the serializer/deserializer (SERDES) accepts 10-bit wide 8b/10b parallel
encoded data bytes. The parallel data bytes are serialized and transmitted differentially at PECL compatible
voltage levels. The SERDES extracts clock information from the input serial stream and deserializes the data,
outputting a parallel 10-bit data byte.
In the DDR mode the parallel interface accepts 5-bit wide 8b/10b encoded data aligned to both the rising and
falling edge of the reference clock. The data is clocked most significant bit first, (bits 0 − 4 of the 8b/10b encoded
data) on the rising edge of the clock and the least significant bits (bits 5 − 9 of the 8b/10b encoded data) are
clocked on the falling edge of the clock.
The device provides a comprehensive series of built-in tests for self-test purposes including loopback and
pseudorandom binary sequence (PRBS) generation and verification. An IEEE 1149.1 JTAG port is also
supported.
The TLK1201I is housed in a high-performance, thermally enhanced, 64-pin VQFP PowerPAD package. Use
of the PowerPAD package does not require any special considerations except to note that the PowerPAD, which
is an exposed die pad on the bottom of the device, is a metallic thermal and electrical conductor. It is
recommended that the device’s PowerPAD be soldered to the thermal land on the board.
The TLK1201I is characterized for operation from −0°C to 70°C (TLK1201), or −40°C to 85°C (TLK1201I).
The TLK1201I uses a 2.5-V supply. The I/O section is 3.3-V compatible. With a 2.5-V supply the chipset is very
power-efficient, dissipating less than 200 mW typical power when operating at 1.25 Gbps.
The TLK1201I is designed to be hot plug capable. A power-on reset causes RBC0, RBC1, the parallel output
signal terminals, TXP, and TXN to be held in a high-impedance state.
differences between TLK1201/TLK1201I and TNETE2201
The TLK1201/TLK1201I is the functional equivalent of the TNETE2201. There are several differences between
the devices as noted below. See Figure 12 in the Application Information section for an example of a typical
application circuit.
D The V_CC is 2.5 V for the TLK1201 vs 3.3 V for TNETE2201.
D The PLL filter capacitors on pins 16, 17, 48, and 49 of the TNETE2201 are no longer required. The TLK1201
uses these pins to provide added test capabilities. The capacitors, if present, do not affect the operation
of the device.
D No pulldown resistors are required on the TXP/TXN outputs.
T_A
−0°C to 70°C
−40°C to 85°C
AVAILABLE OPTIONS
PACKAGE
PLASTIC QUAD FLAT PACK
(RCP)
TAPE and REEL OPTION
TLK1201RCP
TLK1201RCPR
TLK1201IRCP
TLK1201IRCPR
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