TLC5620C_08 Datasheet, PDF (2/17 Pages) Texas Instruments – QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS

TLC5620C, TLC5620I
QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS081E – NOVEMBER 1994 – REVISED NOVEMBER 2001
functional block diagram
2
REFA
+
–
REFB ³
+
–
4
REFC
+
–
5
REFD
+
–
8 _Latch
8 _Latch
8 _Latch
8 _Latch
DAC
Latch
8
×2
DAC
Latch
8
×2
DAC
Latch
8
×2
DAC
Latch
8
×2
CLK ⁷
DATA ⁶
LOAD ⁸
Serial
Interface
13
LDAC
Power-On
Reset
+
12
DACA
–
+
11 _DACB
–
+
–
10 _DACC
+
9 _DACD
–
Terminal Functions
TERMINAL
NAME NO.
CLK
7
DACA
12
DACB
11
DACC
10
DACD
9
DATA
6
GND
1
LDAC
13
LOAD
8
REFA
2
REFB
3
REFC
4
REFD
5
VDD
14
I/O
DESCRIPTION
I Serial interface clock. The input digital data is shifted into the serial interface
register on the falling edge of the clock applied to the CLK terminal.
O DAC A analog output
O DAC B analog output
O DAC C analog output
O DAC D analog output
I Serial interface digital data input. The digital code for the DAC is clocked into the
serial interface register serially. Each data bit is clocked into the register on the
falling edge of the clock signal.
I Ground return and reference terminal
I Load DAC. When the LDAC signal is high, no DAC output updates occur when
the input digital data is read into the serial interface. The DAC outputs are only
updated when LDAC is taken from high to low.
I Serial Interface load control. When LDAC is low, the falling edge of the LOAD
signal latches the digital data into the output latch and immediately produces the
analog voltage at the DAC output terminal.
I Reference voltage input to DAC A. This voltage defines the output analog range.
I Reference voltage input to DAC B. This voltage defines the output analog range.
I Reference voltage input to DAC C. This voltage defines the output analog range.
I Reference voltage input to DAC D. This voltage defines the output analog range.
I Positive supply voltage
2
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