TLC5502-5M Datasheet, PDF (2/11 Pages) Texas Instruments – 8-BIT ANALOG-TO-DIGITAL CONVERTER

TLC5502Ć5M
8ĆBIT ANALOGĆTOĆDIGITAL CONVERTER
SGLS067 − MARCH 1992
functional block diagram
10
CLK
19, 20
ANLG INPUT
REFT ¹⁷
1
R1
2
R
R
R/2
18
REFM
R/2
127
255-to-8
Encoder
128
254
R
255
R
R2
21
REFB
EN
Latch
and
Buffer
9
D7 (MSB)
8
D6
7
D5
6
D4
5
D3
4
D2
3
D1
2
D0 (LSB)
operating sequence
CLK
ANALOG
INPUT
D0−D7
Sample
N
Data
N−1
Sample
N+1
td
Data
N
Sample
N+2
Data
N+1
Following the operating sequence above, the rising edge of the clock samples the analog input (sample N) at
time t_N and latches sample N−1 at the output. Sample N is encoded to eight digital lines on the next falling edge
of the clock and then the following high clock level latches these eight bits to the outputs (with a delay t_d) and
acquires sample N + 1. Conversion is completed in one clock cycle and continues the sequence for the next
cycle.
4−180
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