SN74SSTVF16857_09 Datasheet, PDF (2/12 Pages) Texas Instruments – 14 BIT REGISTERED BUFFER WITH SSTL 2 INPUT AND OUTPUTS

SN74SSTVF16857
14ĆBIT REGISTERED BUFFER
WITH SSTL_2 INPUTS AND OUTPUTS
SCES411B – AUGUST 2002 – REVISED APRIL 2003
description/ordering information (continued)
The device supports low-power standby operation. When RESET is low, the differential input receivers are
disabled, and undriven (floating) data, clock, and reference voltage (V_REF) inputs are allowed. In addition, when
RESET is low, all registers are reset, and all outputs are forced low. The LVCMOS RESET input always must
be held at a valid logic high or low level.
To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in
the low state during power up.
FUNCTION TABLE
RESET
INPUTS
CLK
CLK
OUTPUT
D
Q
H
↑
↓
H
H
H
↑
↓
L
L
H
L or H
L or H
X
Q0
L X, or floating X, or floating X, or floating
L
logic diagram (positive logic)
RESET ³⁴
CLK ³⁸
CLK ³⁹
VREF ³⁵
D1 ⁴⁸
One of 14 Channels
1D
C1
R
1
Q1
To 13 Other Channels
2
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265