SN74LVC2G126-EP_15 Datasheet, PDF (2/13 Pages) Texas Instruments – DUAL BUS BUFFER GATE WITH 3-STATE OUTPUTS

SN74LVC2G126-EP
SCES856 – DECEMBER 2013
Logic Diagram (Positive Logic)
1
1OE
2
1A
6
1Y
7
2OE
5
2A
3
2Y
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ABSOLUTE MAXIMUM RATINGs⁽¹⁾
over operating free-air temperature range (unless otherwise noted)
MIN
MAX UNIT
V_CC Supply voltage range
V_I
Input voltage range⁽²⁾
V_O Voltage range applied to any output in the high-impedance or power-off state⁽²⁾
V_O Voltage range applied to any output in the high or low state^{(2) (3)}
I_IK Input clamp current
V_I < 0
I_OK Output clamp current
V_O < 0
I_O Continuous output current
Continuous current through V_CC or GND
T_J Absolute maximum junction temperature range
T_stg Storage temperature range
–0.5
6.5 V
–0.5
6.5 V
–0.5
6.5 V
–0.5 V_CC + 0.5 V
–50 mA
–50 mA
±50 mA
±100 mA
–55
150 °C
–65
150 °C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
(3) The value of V_CC is provided in the recommended operating conditions table.
THERMAL INFORMATION
THERMAL METRIC⁽¹⁾
SN74LVC2G126-EP
DCU
UNITS
θ_JA
θ_JCtop
θ_JB
ψ_JT
ψ_JB
θ_JCbot
Junction-to-ambient thermal resistance⁽²⁾
Junction-to-case (top) thermal resistance⁽³⁾
Junction-to-board thermal resistance⁽⁴⁾
Junction-to-top characterization parameter⁽⁵⁾
Junction-to-board characterization parameter⁽⁶⁾
Junction-to-case (bottom) thermal resistance⁽⁷⁾
8 PINS
204.3
78
83
7.6
82.6
N/A
°C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψ_JT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ_JA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψ_JB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ_JA , using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
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