SN74LVC1G10_15 Datasheet, PDF (2/25 Pages) Texas Instruments – Single 3-Input Positive-NAND Gate

SN74LVC1G10
SCES486E – SEPTEMBER 2003 – REVISED DECEMBER 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Function Table
INPUTS
A
B
C
OUTPUT
Y
H
H
H
L
L
X
X
H
X
L
X
H
X
X
L
H
Logic diagram (Positive Logic)
A
B
Y
C
Absolute Maximum Ratings⁽¹⁾
over operating free-air temperature range (unless otherwise noted)
MIN
MAX UNIT
V_CC
Supply voltage range
V_I
Input voltage range⁽²⁾
V_O
Voltage range applied to any output in the high-impedance or power-off state⁽²⁾
V_O
Voltage range applied to any output in the high or low state^{(2) (3)}
I_IK
Input clamp current
V_I < 0
I_OK
Output clamp current
V_O < 0
I_O
Continuous output current
Continuous current through V_CC or GND
DBV package
θ_JA
Package thermal impedance⁽⁴⁾
DCK package
YZP package
–0.5
6.5 V
–0.5
6.5 V
–0.5
6.5 V
–0.5 V_CC + 0.5
V
–50 mA
–50 mA
±50 mA
±100 mA
165
259 °C/W
123
T_stg
Storage temperature range
–65
150 °C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The value of V_CC is provided in the recommended operating conditions table.
(4) The package thermal impedance is calculated in accordance with JESD 51-7.
2
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