SN74LVC10A_15 Datasheet, PDF (2/19 Pages) Texas Instruments – TRIPLE 3-INPUT POSITIVE-NAND GATE

SN74LVC10A
TRIPLE 3-INPUT POSITIVE-NAND GATE
SCAS284O – JANUARY 1993 – REVISED JULY 2005
FUNCTION TABLE
(EACH GATE)
INPUTS
A
B
C
H
H
H
L
X
X
X
L
X
X
X
L
OUTPUT
Y
L
H
H
H
LOGIC DIAGRAM, EACH GATE (POSITIVE LOGIC)
A
B
Y
C
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Absolute Maximum Ratings ⁽¹⁾
over operating free-air temperature range (unless otherwise noted)
V_CC
Supply voltage range
V_I
Input voltage range⁽²⁾
V_O
Output voltage range⁽²⁾⁽³⁾
I_IK
Input clamp current
I_OK
Output clamp current
I_O
Continuous output current
Continuous current through V_CC or GND
θ_JA
Package thermal impedance
T_stg
Storage temperature range
P_tot
Power dissipation
V_I < 0
V_O < 0
D package ⁽⁴⁾
DB package⁽⁴⁾
NS package⁽⁴⁾
PW package⁽⁴⁾
RGY package⁽⁵⁾
T_A = –40°C to 125°C⁽⁶⁾⁽⁷⁾
MIN
MAX
–0.5
6.5
–0.5
6.5
–0.5 V_CC + 0.5
–50
–50
±50
±100
86
96
76
113
47
–65
150
500
UNIT
V
V
V
mA
mA
mA
mA
°C/W
°C
mW
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The value of V_CC is provided in the recommended operating conditions table.
(4) The package thermal impedance is calculated in accordance with JESD 51-7.
(5) The package thermal impedance is calculated in accordance with JESD 51-5.
(6) For the D package: above 70°C, the value of P_tot derates linearly with 8 mW/K.
(7) For the DB, NS, and PW packages: above 60°C, the value of P_tot derates linearly with 5.5 mW/K.
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