SN74AUP2G04 Datasheet, PDF (2/20 Pages) Texas Instruments – LOW-POWER DUAL INVERTER GATE

SN74AUP2G04
SCES747B – SEPTEMBER 2009 – REVISED MARCH 2010
www.ti.com
NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the
package.
This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
T_A
–40°C to 85°C
ORDERING INFORMATION⁽¹⁾
PACKAGE ⁽²⁾
ORDERABLE
PART NUMBER
NanoStar™ – WCSP (DSBGA)
0.23-mm Large Bump – YFP (Pb-free)
Reel of 3000
SN74AUP2G04YFPR
QFN – DRY
Reel of 5000
SN74AUP2G04DRYR
uQFN – DSF
Reel of 5000
SN74AUP2G04DSFR
SOT (SC-70) – DCK
Reel of 3000
SN74AUP2G04DCKR
TOP-SIDE
MARKING ⁽³⁾
___HC_
H4
H4
H4_
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(3) DCK: The actual top-side marking has one additional character that designates the wafer fab/assembly site.
YFP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the wafer fab/assembly site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).
FUNCTION TABLE
(Each Inverter)
INPUT
A
OUTPUT
Y
H
L
L
H
LOGIC DIAGRAM (POSITIVE LOGIC)
1
1A
6
1Y
3
2A
4
2Y
2
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