SN65LVDT14-EP Datasheet, PDF (2/19 Pages) Texas Instruments – Memory Stick INTERCONNECT EXTENDER CHIPSET WITH LVDS

SN65LVDT14-EP, SN65LVDT41-EP
SCES633 – JUNE 2005
www.ti.com
SN65LVDT41 LOGIC DIAGRAM
(POSITIVE LOGIC)
SN65LVDT14 LOGIC DIAGRAM
(POSITIVE LOGIC)
1Y
1D
1Z
2Y
2D
2Z
3Y
3D
3Z
4Y
4D
4Z
5A
5R
5B
1A
1R
1B
2A
2R
2B
3A
3R
3B
4A
4R
4B
5Y
5D
5Z
TYPICAL MEMORY STICK INTERFACE EXTENSION
SN65LVDT41
SN65LVDT14
SCLK
Memory
Stick ^BS
Host _SDIO
Controller _DIR
1D
1Y
SCLK
1A
1R
1Z
1B
SCLK
2Y
2D
BS
2Z
2A
2R
2B
Memory
BS _Stick
3Y
3D
DIR
3Z
3A
3R
3B
SDIO
4Y
4D
SD1
4Z
4A
4R
CBT
4B
5A
5Y
CBT 5R
SD2
5D
5B
5Z
Absolute Maximum Ratings⁽¹⁾
over operating free-air temperature range (unless otherwise noted)
V_CC Supply voltage range⁽²⁾
Input voltage range
D or R
A, B, Y, or Z
Electrostatic discharge
Human-Body Model⁽³⁾
Charged-Device Model⁽⁴⁾
Continuous total power dissipation
Storage temperature range
Lead temperature 1,6 mm (1/16 in) from case for 10 s
A, B, Y, Z, and GND
All pins
All pins
SN65LVDT14,
SN65LVDT41
MIN
MAX
UNIT
–0.5
4V
–0.5
6
V
–0.5
4
±12
KV
±8
±500 V
See Dissipation Rating Table
–65
150 °C
260 °C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
(3) Tested in accordance with JEDEC Standard 22, Test Method A114-A
(4) Tested in accordance with JEDEC Standard 22, Test Method C101
2