OPA192 Datasheet, PDF (2/35 Pages) Texas Instruments – High Voltage, Rail-to-Rail Input/Output, Precision Operational Amplifiers, e-trim Series

OPA192
OPA2192
OPA4192
SBOS620A – DECEMBER 2013 – REVISED JANUARY 2014
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGE AND ORDERING INFORMATION⁽¹⁾
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the
device product folder at www.ti.com.
ABSOLUTE MAXIMUM RATINGS⁽¹⁾
Over operating free-air temperature range, unless otherwise noted.
Supply voltage
Signal input
terminals
Voltage
Current
Output short circuit⁽²⁾
Common-mode
Differential
Operating temperature
Storage temperature
Junction temperature
Electrostatic
discharge (ESD)
ratings
Human body model (HBM)
Charged device model (CDM)
VALUE
±20 (+40, single supply)
(V–) – 0.5 to (V+) + 0.5
(V+) - (V-) + 0.2
±10
Continuous
–55 to +150
–65 to +150
+150
4
1
UNIT
V
V
V
mA
°C
°C
°C
kV
kV
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
(2) Short-circuit to ground, one amplifier per package.
ELECTRICAL CHARACTERISTICS: V_S= ±4 V to ±18 V (V_S= +8 V to +36 V)
At T_A = +25°C, V_CM = V_OUT = V_S / 2, and R_LOAD = 10 kΩ connected to V_S / 2, unless otherwise noted.
OPA192
PARAMETER
TEST CONDITIONS
MIN
TYP
OFFSET VOLTAGE
±5
V_OS
Input offset voltage
T_A = –40°C to +125°C
dV_OS/dT Input offset voltage drift T_A = –40°C to +125°C
(V–) – 0.1 V < V_CM < (V+) – 3 V
±0.2
PSRR
Power-supply rejection
ratio
T_A = –40°C to +125°C
±0.3
INPUT BIAS CURRENT
±5
I_B
Input bias current
T_A = –40°C to +125°C
±2
I_OS
Input offset current
T_A = –40°C to +125°C
NOISE
(V–) – 0.1 V < V_CM < (V+) – 3V f = 0.1 Hz to 10 Hz
E_n
Input voltage noise
(V+) – 1.5 V < V_CM < (V+) + 0.1
V
f = 0.1 Hz to 10 Hz
1.30
4
f = 100 Hz
10.5
e_n
Input voltage noise
density
(V–) – 0.1 V < V_CM < (V+) – 3 V
(V+) – 1.5 V < V_CM < (V+) + 0.1
f = 1 kHz
f = 100 Hz
5.5
32
V
f = 1 kHz
12.5
i_n
Input current noise
density
f = 1kHz
1.5
MAX UNIT
±25
µV
±75
µV
±0.5 µV/°C
±1.0
µV/V
±20
pA
±5
nA
±20
pA
±2
nA
µV_PP
µV_PP
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
fA/√Hz
2
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