LP38841 Datasheet, PDF (2/18 Pages) National Semiconductor (TI) – 0.8A Ultra Low Dropout Linear Regulators Stable with Ceramic Output Capacitors

LP38841
SNVS289B – DECEMBER 2004 – REVISED SEPTEMBER 2006
Connection Diagram
Figure 1. TO-220, Top View
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Figure 2. TO-263, Top View
Pin Functions
Pin Name
BIAS
OUTPUT
GND
INPUT
SHUTDOWN
Block Diagram
Pin Descriptions
Description
The bias pin is used to provide the low current bias voltage to the chip which operates the internal circuitry and
provides drive voltage for the N-FET.
The regulated output voltage is connected to this pin.
This is both the power and analog ground for the IC. Note that both pin three and the tab of the TO-220 and TO-
263 packages are at ground potential. Pin three and the tab should be tied together using the PC board copper
trace material and connected to circuit ground.
The high current input voltage which is regulated down to the nominal output voltage must be connected to this
pin. Because the bias voltage to operate the chip is provided seperately, the input voltage can be as low as a
few hundered millivolts above the output voltage.
This provides a low power shutdown function which turns the regulated output OFF. Tie to V_BIAS if this function is
not used.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
2
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