LM34923 Datasheet, PDF (2/26 Pages) National Semiconductor (TI) – EVAL evaluation board provides the design engineer with a fully

LM34923
SNVS695A – MARCH 2011 – REVISED FEBRUARY 2013
Connection Diagram
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SW
1
BST
2
N/C
3
RTN
4
UV
5
10
VIN
9
VCC
8
RT
7
FB
6
UVO
Figure 1. Top View
10-Lead VSSOP
Pin Name
No.
Description
1
SW Switching Node
2 BST Boost Pin
3
N/C Do not connect
4 RTN Ground pin
5
UV Input pin for the under
voltage indicator
6 UVO Under voltage status
indicator
7
FB Feedback Input from
Regulated Output
8 RT/SD On-time set pin and
shutdown input
9 VCC Output from the internal
high voltage series pass
regulator. Regulated at
7.5V.
10 VIN Input Voltage
Table 1. Pin Descriptions
Application Information
Power switching node. Connect to the output inductor, re-circulating diode or synchronous
FET, and bootstrap capacitor.
An external capacitor is required between the BST and the SW pins (0.01uF or greater
ceramic). The BST pin capacitor is charged from VCC through an internal diode when SW is
low.
Ground for the entire circuit.
A resistor divider from VIN, or some other system voltage, programs the under-voltage
detection threshold. An internal current sink is enabled when UV is below 2.5V to provide
hysteresis.
This open drain output is high when the UV pin voltage is below 2.5V, or when the VCC_UVLO
function or the shutdown function is invoked.
This pin is connected to the inverting input of the internal regulation comparator. The
regulation level is 2.5V.
A resistor between this pin and Vin sets the switch on-time as a function of Vin, and the
frequency. The minimum recommended on-time is 200 ns at max input voltage. Taking this
pin to ground shuts off the regulator.
The internal regulator provides bias supply for the Buck switch gate driver and other internal
circuitry. A 1uF ceramic capacitor to ground is required. The regulator is current limited to
≈30 mA.
The operating input range is 6V to 75V
2
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