DS91M047_13 Datasheet, PDF (2/16 Pages) Texas Instruments – 125 MHz Quad M-LVDS Line Driver

DS91M047
SNLS145E – JUNE 2008 – REVISED APRIL 2013
Connection Diagrams
DE
1
DI0
2
DI1
3
VDD
4
GND
5
DI2
6
DI3
7
DE
8
16
B0
15
A0
14
A1
13
B1
12
B2
11
A2
10
A3
9
B3
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DE
DE
B0
DI0
A0
B1
DI1
A1
B2
DI2
A2
B3
DI3
A3
Pin No.
2, 3, 6, 7
10, 11, 14, 15
9, 12, 13, 16
1
8
4
5
Name
DI
A
B
DE
DE
V_DD
GND
PIN DESCRIPTIONS
Description
Driver input pin, LVCMOS compatible.
Non-inverting driver output pin, M-LVDS levels.
Inverting driver output pin, M-LVDS levels.
Driver enable pin: When DE is low, the driver is disabled. When DE is high and DE is low or open, the
driver is enabled. If both DE and DE are open circuit, then the driver is disabled.
Driver enable pin: When DE is high, the driver is disabled. When DE is low or open and DE is high, the
driver is enabled. If both DE and DE are open circuit, then the driver is disabled.
Power supply pin, +3.3V ± 0.3V
Ground pin
TRUTH TABLE
Enables
DE
DE
H
L
All other combinations of ENABLE inputs
Input
DI
L
H
X
Outputs
A
B
L
H
H
L
Z
Z
2
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