DS90CP02_14 Datasheet, PDF (2/15 Pages) Texas Instruments – DS90CP02 1.5 Gbps 2x2 LVDS Crosspoint Switch

DS90CP02
SNLS267 – NOVEMBER 2008
Pin
Name
Pin
Number
I/O, Type
IN0+
IN0−
9
I, LVDS
10
IN1+
IN1−
12
I, LVDS
13
SWITCHED DIFFERENTIAL OUTPUTS
OUT0+
27
O, LVDS
OUT0−
26
OUT1+
24
O, LVDS
OUT1−
23
DIGITAL CONTROL INTERFACE
SEL0, SEL1
6
5
I, LVTTL
EN0, EN1
7
15
I, LVTTL
N/C
8, 20, 28
POWER
V_DD
11, 14, 16,
I, Power
18, 19, 22,
25
GND
DAP, 1, 2,
3, 4, 17,
21
I, Power
Connection Diagram
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Pin Descriptions (continued)
Description
Inverting and non-inverting differential inputs. LVDS, Bus LVDS, CML, or LVPECL
compatible.
Inverting and non-inverting differential inputs. LVDS, Bus LVDS, CML, or LVPECL
compatible.
Inverting and non-inverting differential outputs. OUT0± can be connected to any one pair
IN0±, or IN1±. LVDS compatible .
Inverting and non-inverting differential outputs. OUT1± can be connected to any one pair
IN0±, or IN1±. LVDS compatible .
Select Control Inputs
Output Enable Inputs
Not Connected
V_DD = 3.3V ±0.3V. At least 4 low ESR 0.01 µF bypass capacitors should be connected from
V_DD to GND plane.
Ground reference to LVDS and CMOS circuitry.
For the LLP package, the DAP is used as the primary GND connection to the device. The
DAP is the exposed metal contact at the bottom of the LLP-28 package. It should be
connected to the ground plane with at least 4 vias for optimal AC and thermal performance.
N/C
IN0+
IN0-
VDDA
IN1+
IN1-
VDD
7654321
8
28
9
27
10
26
11
DAP
25
(GND)
12
24
13
23
14
22
15 16 17 18 19 20 21
N/C
OUT0+
OUT0-
VDDA
OUT1+
OUT1-
VDD
Figure 2. LLP Top View
DAP = GND
Configuration Select Truth Table
SEL0
SEL1
EN0
EN1
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
0
0
1
0
1
OUT0
IN0
IN0
IN1
IN1
IN0
OUT1
IN0
IN1
IN0
IN1
PD
Mode
1:2 Splitter (IN1 powered down)
Dual Channel Repeater
Dual Channel Switch
1:2 Splitter (IN0 powered down)
Single Channel Repeater (Channel 1 powered down)
2
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