CD54HC74_14 Datasheet, PDF (2/17 Pages) Texas Instruments – Dual D Flip-Flop with Set and Reset

CD54HC74, CD74HC74, CD54HCT74, CD74HCT74
Pinout
CD54HC74, CD54HCT74
(CERDIP)
CD74HC74, CD74HCT74
(PDIP, SOIC)
TOP VIEW
1R 1
1D 2
1CP 3
1S 4
1Q 5
1Q 6
GND 7
14 V_CC
13 2R
12 2D
11 2CP
10 2S
9 2Q
8 2Q
Functional Diagram
1
RESET
2
DATA
3
CLOCK
4
SET
13
RESET
12
DATA
11
CLOCK
10
SET
R
D
F/F 1
CP
S
R
D
F/F 2
CP
S
5
Q
6
Q
9
Q
8
Q
GND = PIN 7
V_CC = PIN 14
TRUTH TABLE
INPUTS
OUTPUTS
SET
RESET
CP
D
Q
Q
L
H
X
X
H
L
H
L
X
X
L
H
L
L
X
X
H (Note 1)
H (Note 1)
H
H
↑
H
H
L
H
H
↑
L
L
H
H
H
L
X
Q0
Q0
H= High Level (Steady State)
L= Low Level (Steady State)
X= Don’t Care
↑= Low-to-High Transition
Q0 = the level of Q before the indicated input conditions were established.
NOTE:
1. This configuration is nonstable, that is, it will not persist when set and reset inputs return to their inactive (high) level.
2