ADC104S051CIMM Datasheet, PDF (2/25 Pages) Texas Instruments – ADC104S051 4 Channel, 200 ksps to 500 ksps, 10-Bit A/D Converter

ADC104S051
SNAS253G – NOVEMBER 2004 – REVISED MARCH 2013
Block Diagram
IN1
.
.
MUX
.
IN4
T/H
GND
10-Bit
SUCCESSIVE
APPROXIMATION
ADC
V_A
GND
CONTROL
LOGIC
SCLK
CS
DIN
DOUT
www.ti.com
Pin No.
ANALOG I/O
4-7
DIGITAL I/O
10
9
8
1
POWER SUPPLY
2
3
PIN DESCRIPTIONS and EQUIVALENT CIRCUITS
Symbol
Description
IN1 to IN4
SCLK
DOUT
DIN
CS
Analog inputs. These signals can range from 0V to V_A.
Digital clock input. This clock directly controls the conversion and readout processes.
Digital data output. The output samples are clocked out of this pin on falling edges of the
SCLK pin.
Digital data input. The ADC104S051's Control Register is loaded through this pin on rising
edges of the SCLK pin.
Chip select. On the falling edge of CS, a conversion process begins. Conversions continue
as long as CS is held low.
V_A
GND
Positive supply pin. This pin should be connected to a quiet +2.7V to +5.25V source and
bypassed to GND with a 1 µF capacitor and a 0.1 µF monolithic capacitor located within 1
cm of the power pin.
The ground return for the supply and signals.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
2
Submit Documentation Feedback
Copyright © 2004–2013, Texas Instruments Incorporated
Product Folder Links: ADC104S051