ADC082S051_14 Datasheet, PDF (2/29 Pages) Texas Instruments – 2 Channel, 200 ksps to 500 ksps, 8-Bit A/D Converter

ADC082S051
SNAS263F – NOVEMBER 2004 – REVISED MARCH 2013
Block Diagram
IN1
MUX
IN2
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T/H
GND
8-BIT
SUCCESSIVE
APPROXIMATION
ADC
V_A
GND
CONTROL
LOGIC
SCLK
CS
DIN
DOUT
Pin No.
ANALOG I/O
5,4
DIGITAL I/O
8
7
6
1
POWER SUPPLY
2
3
Pin Descriptions and Equivalent Circuits
Pin Name
Description
IN1 and IN2
SCLK
DOUT
DIN
CS
Analog inputs. These signals can range from 0V to V_A.
Digital clock input. This clock directly controls the conversion and readout processes.
Digital data output. The output samples are clocked out of this pin on falling edges of the
SCLK pin.
Digital data input. The ADC082S051's Control Register is loaded through this pin on rising
edges of the SCLK pin.
Chip select. On the falling edge of CS, a conversion process begins. Conversions continue
as long as CS is held low.
V_A
GND
Positive supply pin. This pin should be connected to a quiet +2.7V to +5.25V source and
bypassed to GND with a 1 µF capacitor and a 0.1 µF monolithic capacitor located within 1
cm of the power pin.
The ground return for the die.
2
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