TVP3026M_12 Datasheet, PDF (19/97 Pages) Texas Instruments – Video Interface Palette

Table 2–5. Clock Selection Register Bits CSR(6 – 4)
(Index: 0x1A, Access: R/W, Default: 0x07)
CLOCK SELECT REGISTER BITS
6
5
4
VCLK FREQUENCY
0
0
0
Dot clock
0
0
1
Dot clock/2
0
1
0
Dot clock/4
0
1
1
Dot clock/8
1
0
0
Dot clock/16
1
0
1
Dot clock/32
1
1
0
Dot clock/64
1
1
1
Reset to 0
NOTE 2: Bit CSR7 enables the SCLK output when set to 1.
Table 2–6. Clock Selection Register Bits CSR(3 – 0) (Index: 0x1A, Access: R/W, Default: 0x07)
CLOCK SELECT REGISTER BITS
3
2
1
0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
X
X
X
x = do not care
FUNCTION
Select CLK0 as clock source (for use with LCLK latching of VGA port). See
subsection 2.6.2, VGA Modes.
Select CLK1 as clock source
Select CLK2 as TTL clock source
Select CLK2 as TTL clock source
Select CLK2 and CLK2 as ECL clock source
Select pixel clock PLL as clock source
Disable internal dot clock for reduced power consumption.
Select CLK0 as clock source (for use with CLK0 latching of VGA port). See
subsection 2.6.2, VGA Modes.
Reserved
2.4 PLL Clock Generators
In addition to externally supplied clock sources, the TVP3026M has three on-chip, fully programmable,
frequency-synthesis phase-locked loops (PLLs). The first PLL, pixel clock, is intended for pixel clock
generation for frequencies up to the device limit. The second PLL, MCLK, is provided for general system
clocking such as the system clock or memory clock, and the third PLL ,called the loop clock PLL, is useful
for synchronizing pixel data and latch timing by compensating for system loop delay.
The clock generators use a modified M over (N × 2^P) scheme to enable a wide range of precise frequencies.
(Appendix A provides a listing of all frequencies that can be synthesized and the register values for each.)
The advanced PLLs utilize an internal loop filter to provide maximum noise immunity and minimum jitter.
Except for the reference crystal or oscillator, no external components or adjustments are necessary. Each
PLL can be independently enabled or disabled for maximum system flexibility. Figure 2–1 illustrates the
TVP3026M PLL clocking scheme. The PLLs are programmed through a group of four registers in the
TVP3026M indirect register map. The registers are listed in Table 2–7.
2–6