TPS92515 Datasheet, PDF (19/39 Pages) Texas Instruments – 2-A, Buck LED Driver with Integrated N-channel FET,High-Side Current Sense, and Shunt FET PWM Dimming Capability

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BOOT
UVLO
TPS92515, TPS92515-Q1, TPS92515HV, TPS92515HV-Q1
SLUSBZ6A – APRIL 2016 – REVISED AUGUST 2016
Internal
N-FET
Gate
DRN
SW
BOOT
VCCUVLO
5 mA
100 µA
VCC
PWM
Figure 25. BOOT and PWM Pull-Downs
8.3.11 PWM (UVLO and Enable)
If PWM dimming or ON/OFF control is not needed in the application, the pin should be tied to VCC. The pin must
be tied above 1 V if operation is desired.
PWM dimming can be achieved using the PWM pin. A signal above 1 V (typical) and below 900 mV (typical)
when measured at the PWM pin should be used. Standard PWM frequency ranges can also be used (100 Hz to
2 kHz). When using higher frequencies the delays from PWM to gate turn ON and turn OFF can begin to limit the
achievable duty cycle.
For example, the PWM to gate delay (turn on + turn off ≈ 100 ns) and the time to slew the switchnode up and
down (approximately 100 ns) total approximately 200 ns.
For example, if a 10 kHz PWM frequency is desired having a period of 100 μs, the minimum duty cycle is 200
ns/100 μs = 0.2%. This is sometimes referred to as "500:1 dimming". As the PWM signal width becomes smaller,
the converter ON and OFF time are eventually controlled by the PWM input signal directly. For example, if the
PWM ON-time is shorter than the converter natural demanded ON-time, the PWM signal itself becomes the
control signal for the high-side switch. The PWM pin activates a weak pulldown, as shown in Figure 25. Because
the PWM pin is also UVLO (undervoltage lockout and device enable), when pulled low it is necessary to ensure
the output is 100% OFF. The high-side FET driver has a small leakage path to the output. Although very small
(<<100μA), theLEDs could glow if the current was not eliminated. The 100-μA (typical) pulldown is activated and
held ON while PWM is low and ensures no light output.
8.3.11.1 Using PWM for UVLO (Undervoltage Lockout) Protection
When the PWM pin exceeds the 1-V (typical) threshold, the device activates a 100-mV (typical) fixed hysteresis
and an adjustable hysteresis based on an internal current source (I_{PWM(uvlo-hys)}). This functionality provides noise
immunity to the PWM control and adjustability to the UVLO hysteresis. The two thresholds can be designed as
described in the UVLO Programming Resistors section.
8.3.11.1.1 UVLO Programming Resistors
The value of resistors R2 and R3 establish the undervoltage lockout level as shown in Figure 26. Include a small
level of capacitance (approximately 0.1 µF) at the UVLO pin for noise immunity. If the application does not
require drop-out operation (operation when V_IN approximates V_LED) program a UVLO level allows no switching to
occur until there is adequate input voltage available.
Copyright © 2016, Texas Instruments Incorporated
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