TPS546C23 Datasheet, PDF (19/97 Pages) Texas Instruments – 4.5-V to 18-V, 35-A Stackable Synchronous Buck Converters With PMBus

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TPS546C23
SLUSCC7A – JULY 2016 – REVISED AUGUST 2016
V_{RESET_B}
V_OUT
Pre-AVS V_OUT
(A)
Default
Output Voltage _.
(B)
Response Delay
Time
A. VOUT_COMMAND adjustment occurs through the PMBus interface.
B. Reset to the default VOUT_COMMAND value which is latched when the devices are powered up from AVIN. The
slew rate is defined by the VOUT_TRANSITION_RATE comand.
Figure 26. Output Voltage Reset
7.3.9 Switching Frequency and Synchronization
A resistor from the RT pin (R_RT) to AGND sets the switching frequency. Use Equation 4 to calculate the R_RT
resistor value.
2.01 × 10¹⁰
R_RT =
f_SW
where
• R_RT is the timing resistor in Ohms
• f_SW is the switching frequency in Hertz
(4)
The devices are designed to operate from 200 kHz to 1 MHz.
7.3.9.1 Synchronization
The devices can synchronize to an external clock that is ±20% of the free-running frequency.
7.3.9.1.1 Stand-Alone Device
The device supports auto detection on the SYNC pin of the stand-alone device or the PWM-loop master device
in a 2-phase configuration. With the external clock applied to the SYNC pin before AVIN power-up or pulling up
the SYNC pin to the BP3 or BP6 pin, the SYNC pin is configured as SYNC-IN, and is synchronized to the rising
edge of the external clock applied to this pin, with a minimum pulse width of 200 ns (maximum). If no external
clock edges occur or logic-high voltage is applied to the SYNC pin at AVIN power-up, the SYNC pin is configured
as SYNC-OUT, and the internal free-running frequency set by the RT resistor is output on the SYNC pin. A
sudden change in synchronization clock frequency causes an associated control-loop response, resulting in an
overshoot or undershoot on the output voltage.
7.3.9.1.2 Master-Slave Configuration
Without the requirement of an external clock, the SYNC pin of the PWM-loop master device can be configured as
SYNC-OUT and output a 50% duty-cycle clock to the slave device. The slave device is then synchronized to the
falling edge of the clock applied to the SYNC pin. Both the loop master and slave devices require an RT resistor
to set the free-running frequency. Figure 27 shows the simplified schematic for this configuration. For the loop
slave device in a 2-phase configuration, the SYNC pin is always configured as SYNC-IN, and is synchronized to
the falling edge of the incoming clock on the SYNC pin. Figure 28 shows the timing for phase interleaving.
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