TPS43330-Q1_14 Datasheet, PDF (19/48 Pages) Texas Instruments – Low IQ, Single Boost, Dual Synchronous Buck Controller

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TPS43330-Q1, TPS43332-Q1
SLVSA82F – MARCH 2011 – REVISED DECEMBER 2014
Feature Description (continued)
9.3.1.7 Power-Good Outputs and Filter Delays
Each buck controller has an independent power-good comparator monitoring the feedback voltage at the FBx
pins and indicating whether the output voltage has fallen below a specified power-good threshold. This threshold
has a typical value of 93% of the regulated output voltage. The power-good indicator is available as an open-
drain output at the PGx pins. An internal 50-kΩ pullup resistor to Sx2 is available, or use of an external resistor is
possible. Shutdown of a buck controller causes an internal pulldown of the power-good indicator. Connecting the
pullup resistor to a rail other than the output of that particular buck channel causes a constant current flow
through the resistor when the buck controller is powered down.
To avoid triggering the power-good indicators because of noise or fast transients on the output voltage, the
device uses an internal delay circuit for de-glitching. Similarly, when the output voltage returns to the set value
after a long negative transient, assertion of the power-good indicator (release of the open-drain pin) occurs after
the same delay. Use of this delay can pause the reset of circuits powered from the buck regulator rail. Program
the duration of the delay by using a suitable capacitor at the DLYAB pin according to Equation 4.
t_DELAY
1 msec
=
C_DLYAB
1 nF
(4)
When the DLYAB pin is open, the delay setting is for a default value of 20 µs typical. The power-good delay
timing is common to both the buck rails, but the power-good comparators and indicators function independently.
9.3.2 Boost Controller
The boost controller has a fixed-frequency voltage-mode architecture and includes cycle-by-cycle current-limit
protection for the external N-channel MOSFET. The boost-controller switching-frequency setting is one-half of the
buck-controller switching frequency. An internal resistor-divider network programmable to 7 V, 10 V, or 11 V sets
the output voltage of the boost controller at the VIN pin, based on the low, open, or high status, respectively, of
the DIV pin. The device does not recognize a change of the DIV setting while the in the low-power mode.
The active-high ENC pin enables the boost controller, which is active when the input voltage at the VBAT pin has
crossed the unlock threshold of 8.5 V at least once. A single threshold crossing arms the boost controller, which
begins switching as soon as V_IN falls below the value set by the DIV pin, regulating the VIN voltage. Thus, the
boost regulator maintains a stable input voltage for the buck regulators during transient events such as a
cranking pulse at the VBAT pin.
A voltage at the DS pin exceeding 200 mV pulls the CG1 pin low, turning off the boost external MOSFET.
Connecting the DS pin to the drain of the MOSFET or to a sense resistor between the MOSFET source and
ground achieves cycle-by-cycle overcurrent protection for the MOSFET. Select the on-resistance of the MOSFET
or the value of the sense resistor in such a way that the on-state voltage at DS does not exceed 200 mV at the
maximum-load and minimum-input-voltage conditions. When using a sense resistor, TI recommends connecting
a filter network between the DS pin and the sense resistor for better noise immunity.
The boost output (VIN) can be used to supply other circuits in the system. However, the boost output should be
high-voltage tolerant. The device regulates the boost output to the programmed value only when VIN is low, and
so VIN can reach battery levels.
V_BAT
V_IN
TPS43330-Q1 ^DS
or
TPS43332-Q1
GC1
Figure 17. External Drain-Source Voltage Sensing
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