TLV3691_15 Datasheet, PDF (19/29 Pages) Texas Instruments – 0.9-V to 6.5-V, Nanopower Comparator

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10 Layout
TLV3691
SBOS694A – DECEMBER 2013 – REVISED NOVEMBER 2015
10.1 Layout Guidelines
Comparators are very sensitive to input noise. For best results, adhere to the following layout guidelines.
1. Use a printed-circuit-board (PCB) with a good, unbroken, low-inductance ground plane. Proper grounding
(use of a ground plane) helps maintain specified device performance.
2. To minimize supply noise, place a decoupling capacitor (0.1-μF ceramic, surface-mount capacitor) as close
as possible to V_CC.
3. On the inputs and the output, keep lead lengths as short as possible to avoid unwanted parasitic feedback
around the comparator. Keep inputs away from the output.
4. Solder the device directly to the PCB rather than using a socket.
5. For slow-moving input signals, take care to prevent parasitic feedback. A small capacitor (1000 pF or less)
placed between the inputs can help eliminate oscillations in the transition region. This capacitor causes some
degradation to propagation delay when impedance is low. The topside ground plane runs between the output
and inputs.
6. The ground pin ground trace runs under the device up to the bypass capacitor, shielding the inputs from the
outputs.
10.2 Layout Example
Run the input traces
V+
as far away from
the supply lines
as possible
VIN+
IN+
VCC
GND
To reduce oscillations in the
transition region from very
slow moving input signals, use
a low-ESR, ceramic capacitor
< 1000 pF
VIN-
GND
GND
IN±
OUT
Use low-ESR, ceramic
bypass capacitor. Place
close to device to reduce
parasitic errors
Ground (GND) plane on another layer
Figure 35. TLV3691 Layout Example
VOUT
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